Using C64 Core on MiniMig boards.

[yaqube]

alexh wrote:

There is certainly not enough RAM in the FPGA to implement 16Kbytes (let alone 48Kbytes)... I'll have to look back at it see what I did...

The XC3S400 has 16 RAM blocks of 18K bits each. It gives you 32KB of RAM.

[boing4000]

First of all the core has to be fixed due to some reset and bootup freeze. Then Dirk and I can take care of adding IEC support. Keyboard is already working and provide switching between PAL and NTSC by pressing F12 key.

How compatible the FPGA64 core is to a real C64 I can not say because right now I can't load any game or demo.
The core is using one sram chip of minimig pcb and provide full 64KB of ram! No need to use another fpga blockram. Currently all 3 C64 rom images are stored using blockram, so there are still some space left for some other invention/expansion.

[Palm]

That sounds very nice. But to add another kernal, this must be embedded in the master-binary file (minimig1.bin) right ?
So I need the sources to enbed my own kernal. And the sources are not released, if I understood correctly ?

Boing4000+Dirk: Keep up the good work!!!

Have you thought about how to add cartridge support somehow?
Maybe F11 as freeze-button ? :-) ..or even better: BREAK



Regs
Espen

[boing4000]

Yes to use another kernal the whole core has to be recompiled. Currently the only "external" thing in use is IC7 (sram0) to provide 64KB of memory. everything else like cartridge has to find its place inside the FPGA. This space is very limited as Jakub already said and there is already 13 of 16 blockram in use.

Loading anything else (additional rom image) into sram would require the PIC and a matching file handling. This is too much for me! Im not an expert in FPGA coding, so pls dont expect too much in too little time.
Right now Im very happy to see a working C64 core on minimig. An IEC bus would make this think good enough for me :-)

Lets see what can be done in the future.

[alexh]

yaqube wrote:
The XC3S400 has 16 RAM blocks of 18K bits each. It gives you 32KB of RAM.

Yeah, not quite enough to load 48k ZX Spectrum RAM snapshots via the FPGA IMAGE loading mechanism built into MiniMig's PIC.

Which means :

I never loaded any games (I'm almost sure I did)
I used 16k interface 2 ROM's (Horace goes skiing, PSSST, TransAM etc.) or
I did something else involving the PIC and loading from SD (unlikely as at first my PIC didn't have a bootloader).

[Hojo Norem]

Nice.  How is the video output handled?  It isn't just VGA output it it?  Not interested if it is, unless there's a near perfect PAL emulation filter in there.  I gotta have my low-res blindness to get those extra colours. ^_^

But then again, I guess it should be possible to output a chroma/luma signal from the VGA port, selectable with the scanrate jumper perhaps...

[boing4000]

Currently the core is based on 31KHz at 50/60Hz switchable via F12. to have the same feature as Minimig to select between 15/31KHz by jumper, it has to be adapted into the core. A scandoubler is already there and could maybe be switched on/off. But unlike Minimig the whole system is based on the already doubled frequence, so its not that easy to adapt. Perhaps Dirk and Peter are able to so.
I also would like to see FPGA64 at 15KHz PAL (or NTSC) :-)

[alexh]

I thought that Yaqube's latest MiniMig sources included some sort of filter? Dunno how easy it would be to adapt, credited of course. Some of the more easy filters should be simple to implement from scratch especially having more free space in the FPGA than with an Amiga core.

[Palm]

How is the 64 core doing. ?

Can I ask, is the sources for this available ?

Is it the ISE Foundation 10.1 I need to be able to load a source, compile it and get a binfile ?

Xilinx has a free 60 day eval version, but I am not sure if I need the webpack of the FOundation.

Anyyone who can enlighten me ?


Espen

[mikej]

Peter's original code is available here :

http://www.syntiac.com/fpga64.html

I currently still use ISE 9.2 service pack3 as it, well, works. ISE 10.1 is probably ok but I don't trust new Xilinx software as a general rule.

Webpack is ok for the Spartan3.
http://www.xilinx.com/ise/logic_design_prod/webpack.htm

I don't use the GUI, I provide a batch file which runs the tools. You can practice on my VIC-20 core.
Download,
replace the dummy ROMs with real ROMs in \roms directory
run build_roms.bat (produces VHDL ROM files)
run build_xst.bat

.bit file produced.

You can then modify the .prj and .scr files for the C64 files.
/Mike

[Palm]

Thanks for that info. I will definitely try it out. I just downloaded the webpack 10.1, and I just bought a usb-2-rs232 adapter so I can flash my minimig with new fw aswell, and bought some plexiglass to make a temporary casing for the minimig board to ease the tear on it

I was wondering, do you know how to make a jtag cable or is there a resource on the web to which I can make one ?

Have to drop by work to pick up a adapter so my USB keyboard can be used on the minimig (which only supports ps2 kbd). After that, I will go ahead and try out webpack. This is totally new for me, so it´ll fun.

BTW: Above, you write ".bit file produced". Do you mean ".bin file" (as in, the file I can rename to minimig1.bin and boot up at the minimig) ?


Regs.
Espen

[Chain]

I was wondering, do you know how to make a jtag cable or is there a resource on the web to which I can make one ?

http://www.nuhorizons.com/products/digilent/jtag-cable.html
there are also usb ones, which are definitely faster solution (with par. port its around 6 minutes to push 64kb of code)

[boing4000]

Palm wrote:

I was wondering, do you know how to make a jtag cable or is there a resource on the web to which I can make one ?

BTW: Above, you write ".bit file produced". Do you mean ".bin file" (as in, the file I can rename to minimig1.bin and boot up at the minimig) ?

If you build a .bin file no jtag cable will be required. Just rename the "something_project.bin" after compiling into "minimig1.bin" and store it in root of your (testing) sd-card. Minimig's PIC will upload this file to the fpga and don't care about its contents. Im doing this all the time in testing new fpga64 and minimig core file.

Jtag is a bit faster and no sd-card changing will be necessary. But the cable and fitting software has to be there. Jtag connection will require a .bit file to program the fpga.

[dirkv]

Chain wrote:

there are also usb ones, which are definitely faster solution (with par. port its around 6 minutes to push 64kb of code)

The parallelport Jtag is much faster.
The bitfiles for my Spartan x3s1000 have a size of 403 KB, it tooks nearly 12 seconds to configure the FPGA via par port.
Cheap Xilinx lpt port jtags are available on ebay.
For developing i would prefer always the jtag solution.

Dirk

[boing4000]

Update: IEC bus is working now. Loading via a (selfmade) cable and 1541-II is possible. Games tested so far: Giana Sisters, Airwolf and Arkanoid. All working fine, but scene demo "Deus Ex - Machina" crash while loading the next part. I think is has to do with some kind of speedloader and not yet 100% accurate core timing. Could be fixed in the near future.
Pictures and german information here: click me (If unwanted, I will remove the external link.)

I found it very exciting to do some code + hardwiring and suddenly an external floppy drive is working :-)

[alexh]

At this rate you'll have a release ready in no time ;-)