minimig 4000

[Donar]

According to my tests, the speed is near a 25MHz 040.

Out of interest, which Coldfire and 68k emulator do you use? And what code did you use for testing?

[freqmax]

All 68040 I a have seen are 5V and are hardobtainium. And when a 3.3V (=less pcb, less cost) 75 EUR, 68060 is available. It doesn't make sense to wad into the 5V swamp.

SDRAM is reasonable effort, but DDR2 is a pain to get working due impedance match, risetime considerations etc.. So rather more sdram chips than ddr modules that will proberbly be  more unreliable for electronics hoppyists.

If using PPC is a design decision, Xilinx Virtex is proberbly the most optimal solution (fgpa + cpu in one chop
package)

To get SATA, I have not found any SATA PHY (physcial interface for fpga. So PCI interface seems the most sensible. Possible with a PCI<->Amiga hw translator.

ATX size doesn't imply uggly design per se. You can fit a small board within a larger A4000 case.

Sockets might work on <10MHz Minimig v1.1, but on a >25 MHz A4000 it's deep water. It will distort the signals and hinder any serious performance. SMD soldering is just a fact of life in modern highspeed electronics.

The Coldfire CPU is incompatible in a way that makes it messy to use, Better spend that energy on a m68k verilog/vhdl clone. Which will free a chip and associated support circuitry.

We'r not trying to say it's impossible Just that some issues will have to be resolved before it can continue. And that some choices are more realistic than others.

[downix]

Donar wrote:

According to my tests, the speed is near a 25MHz 040.

Out of interest, which Coldfire and 68k emulator do you use? And what code did you use for testing?

You could make it near native with a hardware translator.

[FrenchShark]

Donar wrote:

According to my tests, the speed is near a 25MHz 040.

Out of interest, which Coldfire and 68k emulator do you use? And what code did you use for testing?

The coldfire : the fastest (MCF548x) : 400 MIPS.
The emulator : my own emulator, it has to run from the internal SRAM of the coldfire. It uses self-modifying code.

[HenryCase]

downix wrote:

HenryCase wrote:

downix said:
If you want the CPU fast-slot I have the design 90% done with my neo-A500 sidecar slot design.

Thanks downix. As it happens it is the A2000 CPU slot that I need for my project. Is this really very similar to the A500 sidecar slot?

I don't want to say too much about my project at the moment, because it might not come to anything, still very early days. When I've got some concrete signs of progress I'll be posting on a.org for assistance.

yes, only 2 pins different.  So, close enough that it can easily be adapted.

That's great news downix. Fingers crossed your Minimig improvement project goes smoothly.

[A6000]

Thank you freqmax for your informative post.

Some considerations that shaped my original post were:-

1. new 060's are expensive if you accept the prices given on freescale's website, so people may want to obtain "pre-owned" 040's or 060's.

2. users may want to walk into their local pc supplier and buy a replacement memory module that will work in the new board, in this respect, SDR modules are in decline, however, the concensus appears to be that SDR chips are the way to go, and I won't argue with that.

3. An open source community project is more likely to produce something that the community wants, rather than what is most profitable but not quite what the users wanted.

[Donar]

You could make it near native with a hardware translator.

You mean a device that translates 68k instructions to the appropriate Coldfire ones,an emulator/translator in HW so to speak?

The emulator : my own emulator, it has to run from the internal SRAM of the coldfire. It uses self-modifying code.

Did you try if it is faster on 68060 optimized code than on average 68k code? From my understanding 060 optimised means less non implemented instructions, so the emulation only would be some kind of "pass through" for these instructions maybe giving more speed.

[rkauer]

 Maybe I'm wrong, but the "newest" 040 of Freescale is 3.3 compliant (don't remember the exact production code), thus is up to 80MHz clockable.

 Can it the useful to Minimig (ok, Maximig instead)?

 I know there will be some issues with libraries (already fixed in the past years), but /me thinks it can be done.

[FrenchShark]

Donar wrote:

Did you try if it is faster on 68060 optimized code than on average 68k code? From my understanding 060 optimised means less non implemented instructions, so the emulation only would be some kind of "pass through" for these instructions maybe giving more speed.

It does not change anything, EVERY instructions are emulated by the emulator. The only impact on the emulator is the use of simple addressing mode vs. complex addressing mode.

[downix]

Donar wrote:

You could make it near native with a hardware translator.

You mean a device that translates 68k instructions to the appropriate Coldfire ones,an emulator/translator in HW so to speak?

Correct.  It is actually the same trick used by both the AMD and Intel CPU's, translating through microcode from the more complex instruction set to a simplified internal one, only we'd be doing it via an external chip.  The 68060 used such a system to it's proto-coldfire core, so much so that my college professor put that the coldfire was just the 060 w/ that translator removed.

[amigadave]

downix wrote:
....  The 68060 used such a system to it's proto-coldfire core, so much so that my college professor put that the coldfire was just the 060 w/ that translator removed.

I am trying to wrap my limited CPU knowledge mind around that statement.  68060 proto-coldfire core???  hmmmm ....  I thought that the coldfire came out after the 68060 and it was a stripped down design with less instructions that met the embedded market demands of the time?

The term 68060 proto-coldfire core sounds to me (the average layman) like a part of the 68060 designed to copy a pre-existing coldfire CPU?  Is this an Egg or the Chicken question, which came first, the 060 or the coldfire?  I guess the coldfire could have as the 68000 series was on its way out and Macs were already moving to the PPC, which is why no Macs ever came from Apple with the 060 inside.

Sorry, just rambling to myself.

[Donar]

It does not change anything, EVERY instructions are emulated by the emulator.

Yes, but for the say 75% percent of the instructions/adressing modes that match on 68060 and Coldfire would it be possible that the/an "emulator" just looks at an:
mov.l an decides to give a mov.l to the Coldfire, having "minimal" performance impact (say 20%)?
For an unimplemented instruction "Z" the emulator could instruct the Coldfire to do Instructions a+b+c giving "Z" thus having a (big) performance hit for these instructions.

I just wonder because Virtual Machines setting up fake CPU's seem to just work in that way (ok they can map every instruction 1:1). As they do not give a big performance hit when you emulate an 4 core system on your 2 core CPU.

[downix]

amigadave wrote:

downix wrote:
....  The 68060 used such a system to it's proto-coldfire core, so much so that my college professor put that the coldfire was just the 060 w/ that translator removed.

I am trying to wrap my limited CPU knowledge mind around that statement.  68060 proto-coldfire core???  hmmmm ....  I thought that the coldfire came out after the 68060 and it was a stripped down design with less instructions that met the embedded market demands of the time?

The term 68060 proto-coldfire core sounds to me (the average layman) like a part of the 68060 designed to copy a pre-existing coldfire CPU?  Is this an Egg or the Chicken question, which came first, the 060 or the coldfire?  I guess the coldfire could have as the 68000 series was on its way out and Macs were already moving to the PPC, which is why no Macs ever came from Apple with the 060 inside.

Sorry, just rambling to myself.

Fundimentally, the 68060 uses a microcode-retranslation system paired up to a reduced-OPcode core, using hardware to translate the instructions that the core cannot natively run into ones that it can.  The majority do just go through, but a few needed translating.  This is how every high-speed CISC CPU has worked since the 68060. In the intel world the first was the NexGen 5x86, for example.  

What my professor theorized was that despite PowerPC taking over the desktop arena, Mot had enough existing 68k customers to support that it turned an eye to how to advance the m68k without hurting it's new PowerPC strategy.  The Motorola engineers basically removed this microcode stage from the m68060 and with a little work, viola, you have the Coldfire.  That way, their performance customers, such as Apple, wouldn't be upset that Motorola was hurting their migration by releasing faster CPU's of the old-family, but Motorolas embedded customers would still get the product they needed.

[amigadave]

@downix,

Great explanation! (even for us laymen) :lol:

I guess I was mostly right in that the coldfire was a stripped down 060 for the embedded market.

[amigadave]

Hmmm, thinking out loud.  Since the Coldfire had that hardware translator removed and since many have wanted to develop a Coldfire accel for the Amiga because of the Coldfire's low cost and availability, as well as its increased speed, maybe we could get Dennis to sit down for another year and develop the missing 68060 part of the Coldfire in an FPGA and we would end up with a real A3000/A4000 Coldfire accelerator that works and runs at 3 to 10 times faster than our old Phase5 060 boards?

If it were that simple, I guess someone would have done it already. :-?

[HenryCase]

amigadave wrote:
Hmmm, thinking out loud.  Since the Coldfire had that hardware translator removed and since many have wanted to develop a Coldfire accel for the Amiga because of the Coldfire's low cost and availability, as well as its increased speed, maybe we could get Dennis to sit down for another year and develop the missing 68060 part of the Coldfire in an FPGA and we would end up with a real A3000/A4000 Coldfire accelerator that works and runs at 3 to 10 times faster than our old Phase5 060 boards?

If it were that simple, I guess someone would have done it already. :-?

amigadave, couple of things:
1. Dennis has already done enough hard work for us on this project already. Anything else we get from him is a huge bonus IMO.
2. TobiFlex has already implemented a Minimig+68000 on FPGA. This solution isn't open source yet but hopefully it will be soon. An A500 wouldn't use the extra instructions of an 68060, right?
3. As we already have a 68000 on FPGA, we could easily overclock it an get some of the speed improvements you are looking for.

There would be two things that limited overclocking; the maximum speed of the FPGA and the clock speed of the Amiga (which we cannot change AFAIK). Some useful overclocking info on this website (http://members.iinet.net.au/~davem2/amiga.html):
"Firstly is the computer being modified of "synchronous" or "asynchonous" design? Synchronous is where the CPU is clocked at a speed which is a direct multiple of the main clock which runs the entire computer."

If the main A500 clock runs at approximately 7.14MHz, we should be able to overclock the 'processor' part of the FPGA to high speeds for an Amiga CPU if we stick to multiples of this base value (121.38MHz, 164.22MHz, etc...). Anyone know what the maximum clock speed for a Spartan-3 FPGA is?