First Start Minimig with FPGA-CPU!!!

[TobiFlex]

Firt time starts a full FPGA-Minimig on the DE2-Board without external CPU and PIC. I use SDRAM and a CPU-IP-CORE. The CPU-Core ist software but not timing kompatible. Thats why make some Demos Problems.

Viele Grüße
TobiFlex

[cv643d]

ok, can I buy one?

[Donar]

Nice, which CPU Core do you use? Maybe the one from wfoerster's Suska project?

[Ohno]

Cool. Very interesting project!

[motorollin]

Can anyone translate this in to English?

--
moto

[freqmax]

@TobiFlex:
If you make a daughterboard with a m68k cpu. You could compare the timing with the HDL "software" cpu.

@motorollin:
It's someone doing what I thought about from the beginning. Implement Minimig with a standard FPGA developer board. That will eliminate the whole manufacturing deal.

A DE-2 board is a FPGA developer board from Altera. Which doesn't provide any Linux version of their Place & Route software as Xilinx & Actel does.

CPU and PIC can be implemented with a HDL computer language. Eliminating the need for actual physical hardware.

http://users.ece.gatech.edu/~hamblen/DE2/
http://www.altera.com/education/univ/materials/boards/unv-dev-edu-boards.html

Cost: 495 USD

http://www.xess.com/prod035.php3
Xilinx Spartan-3 XC3S1000 FPGA with Linux Place & Route software for free.

Cost: 199 USD

[TobiFlex]

I think some day i can fit the Core also into the DE1 Board.

freqmax wrote:
@TobiFlex:
If you make a daughterboard with a m68k cpu. You could compare the timing with the HDL "software" cpu.

This is my way to verfiy the software combatibility. I have developed a CPU-Validator to compare the Hard- and the Soft-CPU. But it is very difficult that the timing will match. At this moment I see no chance.

This CPU-IP-Core has nothing to do with Wolfgangs Core. There are complete different. This is my own development.

Viele Grüße
TobiFlex

[Fantoma]

What sort of resources does it require compared to the Minimig core?  The comparing of Xilinx to Altera gate counts is almost impossible so I guess comparing the synthetic CPU size versus the Minimig core on your setup would give us a clue as to how big it actually is and the minimum size FPGA required to contain it all.  I would imagine the whole thing is too large to fit in a XC3S500E.

[TobiFlex]

Minimig:  6261 LCs + 172060 memory bits
CPU-Core: 3805 LCs
SPIHost:  1938 LCs + 147456 memory bits
others(SDRAM+ Sound) : 300 LCs

[motorollin]

freqmax wrote:
It's someone doing what I thought about from the beginning. Implement Minimig with a standard FPGA developer board. That will eliminate the whole manufacturing deal.

Oh I see. Does that mean we can just order an FPGA dev board off the web, download the MiniMig "code" or whatever the FPGA equivalent is, and have a MiniMig?

--
moto

[alexh]

motorollin wrote:
Oh I see. Does that mean we can just order an FPGA dev board off the web, download the MiniMig "code" or whatever the FPGA equivalent is, and have a MiniMig?

No. You will need to write a board specific wrapper to MiniMig. That could be many weeks work.

[motorollin]

Sure, Dennis' MiniMig code will need to be modified to work on the FPGA dev board. But isn't that what TobiFlex is doing?

--
moto

[Fester]

freqmax wrote:
Implement Minimig with a standard FPGA developer board. That will eliminate the whole manufacturing deal.

A DE-2 board is a FPGA developer board from Altera. [...]

http://users.ece.gatech.edu/~hamblen/DE2/
http://www.altera.com/education/univ/materials/boards/unv-dev-edu-boards.html

Cost: 495 USD

http://www.xess.com/prod035.php3
Xilinx Spartan-3 XC3S1000 FPGA with Linux Place & Route software for free.

Cost: 199 USD

This is a few synaptic connections above my basic stamp 2 projects :-)

But I'm totally interested and would love to tinker with it. Thanks for the links!

[downix]

TobiFlex wrote:
Firt time starts a full FPGA-Minimig on the DE2-Board without external CPU and PIC. I use SDRAM and a CPU-IP-CORE. The CPU-Core ist software but not timing kompatible. Thats why make some Demos Problems.

Viele Grüße
TobiFlex

I just finished checking this option out.  In a word, can't be done.  The EP2C35F672-C6 FPGA it utilizes only has 32,000 gates.  The MiniMig's FPGA is 400,000 and is 80% utilized.  In short, the chipset alone won't fit into the design.

[Lemmink]

Well apart from the question can it be done or not, has anyone looked at the priecetag ? Sheesh 495 $ !!!  :-o