Minimig PCB run - interest thread

[jkonstan]

Doobrey wrote:

Any idea if Freescale's 68306 would work fairly easily? ( straightaway I can see some work needed to convert IPL2:0 to the 306's separate IRQ lines).

Looks like its built in DRAM controller would make adding upto 64MB pretty easy, plus there's some programmable chip selects and IO pins for extra hackable goodness :hammer:

MC68306 could work since it is based on the 68HC000 core.
This is a nice idea (especially with the JTAG port on the MC68306); however, the MC68306 would have issues. The MC68306 DRAM controller works only with old obsolete DRAM which is no longer produced anymore. MC68306 is a 5Volt I/O part; thus, we would have to use level shifters between 5V MC68306 <=> 3.3V FPGA. Thus, there is not as much benefit in using MC68306 as we would like.

 :-)

[jkonstan]

mongo wrote:
Address and Data lines connect to the 68K via level shifters, same with the Reset line. IORD*, IOWR* CS0*, and CS1* can easily be generated completely externally, though you can reduce the number of external components if you use one output line of the FPGA as a IDE Chip Select line. IORDY has to go to the FPGA for it to generate wait states for the 68K if needed, but even that might not be totally necessary unless you plan on using a really old drive. INTRQ has to go to the FPGA, unless you want to poll the drive instead of using interrupts, but I don't recommend doing that if you don't have to.

DMARQ, DMACK, ICS16*, and DASP* aren't needed.

3 FPGA I/O pins and a few external components are all that are required.

Your description shows that you need more than the 4 programmable FPGA Spare I/O pins that are left on MiniMIG Ver1.0 J9 header in order to build the IDE interface that you described and that the MiniMIG PCB would need a new PCB layout. Of course if you add a CPLD/external logic and a bunch of level shifters to MiniMIG, a PIO mode IDE interface could be built.

PI/O IDE is ok; however, DMA can be nice when one can DMA directly into SRAM. Thus, I would not write off the need for DMAREQ and DMACK.

IORDY for IDE would be nice when some users trys to hook there old small IDE hardrives from their old Amigas onto a MiniMIG at some point.

  :-)

[Doobrey]

jkonstan wrote:
 MC68306 is a 5Volt I/O part; thus, we would have to use level shifters between 5V MC68306 <=> 3.3V FPGA. Thus, there is not as much benefit in using MC68306 as we would like.
 

Bummer
 I couldn't see anything in the datasheet that specifically said it was a 5v part.( Or rather, I couldn't see a minimum Vcc in the DC specs..maybe I'm blind).

Ta for the reply.

[mongo]

jkonstan wrote:

Your description shows that you need more than the 4 programmable FPGA Spare I/O pins that are left on MiniMIG Ver1.0 J9 header in order to build the IDE interface that you described and that the MiniMIG PCB would need a new PCB layout. Of course if you add a CPLD/external logic and a bunch of level shifters to MiniMIG, a PIO mode IDE interface could be built.

I need 3 I/O pins and a little external logic to implement an A600/A1200 compatible IDE port, which would allow booting from an IDE hard drive with an appropriate A600 ROM.

I could do it with 2 pins, if I really wanted to.

A new PCB layout is a given if you are going to add IDE.

PI/O IDE is ok; however, DMA can be nice when one can DMA directly into SRAM. Thus, I would not write off the need for DMAREQ and DMACK.

Sure DMA is nice, but it's really not necessary. It also requires new drivers and a separate bus for the IDE, unless you want to shut off the 68K during DMA transfers.

IORDY for IDE would be nice when some users trys to hook there old small IDE hardrives from their old Amigas onto a MiniMIG at some point.

  :-)

I don't have a problem with that. You still don't need more than 3 I/O pins.

[freqmax]

The 68306 product summary only says "Available in 5V". Looking in the datasheets there's no mention of 3.3V. I still fail to see the benefits besides address space. Any DRAM is better controlled by the FPGA where it can be used both as Chip and Fast ram.

If 'TobiFlex' succeeded to use sdram. It would be interesting to find out more in order to replace the 2M Async SRAM with 32-64 MB DRAM or more.

One possible setup is to have two FPGAs and one XCF02S configuration memory.
FPGA0 bootloads configuration from eeprom. And loads data from SD/MMC to configurate FPGA1. FPGA1 loads data from SD/MMC to re-configurate FPGA0. Both bootloaders are deactivated. And normal operation is initiated.
This could allow elimination of the MCU and allow one extra FPGA for m68k vhdl/verilog core. Aswell as plenty of I/O pins to play with.

[jkonstan]

freqmax wrote:
The 68306 product summary only says "Available in 5V". Looking in the datasheets there's no mention of 3.3V. I still fail to see the benefits besides address space. Any DRAM is better controlled by the FPGA where it can be used both as Chip and Fast ram.

If 'TobiFlex' succeeded to use sdram. It would be interesting to find out more in order to replace the 2M Async SRAM with 32-64 MB DRAM or more.

One possible setup is to have two FPGAs and one XCF02S configuration memory.
FPGA0 bootloads configuration from eeprom. And loads data from SD/MMC to configurate FPGA1. FPGA1 loads data from SD/MMC to re-configurate FPGA0. Both bootloaders are deactivated. And normal operation is initiated.
This could allow elimination of the MCU and allow one extra FPGA for m68k vhdl/verilog core. Aswell as plenty of I/O pins to play with.

Use of the dual FPGA scheme could get us more free/open FPGA I/O pins and potentially replace the PIC. The soft 68K CPU core or an additional soft Microblaze CPU could control the SD card as well. In order to lower the cost of the Xilinx FPGAs and expensive Xilinx Configuration serial device, the use of the Spartan3E FPGA which is lower cost and can use  lower cost SPI FLASH (ATMEL, ST, and Spansion) for configuration should be considered (see App note below).

http://www.xilinx.com/bvdocs/appnotes/xapp445.pdf

Also, maybe TobiFlex will share some of his FPGA SD card (floppy replacement)development so that we do not have to re-invent it.

 :-)

[freqmax]

Looking at the core files, only LVCMOS33 is used. So using XC3S500E would be feasable. Any cons/pros of using LVTTL instead?
And 622+ Mbit/s operation is possible between FPGAs.
More config eeprom choices seems to translate into easier to source and lower price.

[downix]

Hmm, if this is the price, I'd consider it.

[AJCopland]

Hi Xenepp,

I'd like one bare board and one assembled please.

Andy

[JimS]

I was just on the schmartboard web site t'other day. They have a prototyping board for BGA chips up to 400 pins. They claim it can be hand-soldered.

[alexh]

Impossible, they must have a BGA rework station.

[Xenepp]

Another update, Dennis alerted me to V1.1 yesterday and I sent it off to China already.

Two weeks and thing will start to happen here! :-D

 -Joel

[JimS]

alexh wrote:
Impossible, they must have a BGA rework station.

Well, they do say that it works better with a reflow oven. However, they do show instructions for doing it by hand.

[freqmax]

The largest Xilinx Spartan-3 FPGA that has less than 400 pins (20x20 matrix) is the FG320 package:
http://direct.xilinx.com/bvdocs/publications/ds099.pdf
(FG320 XC3S1500 is also the largest FPGA with Webpack support)

The FG320 package is an 18x18 matrix with 1mm pitch:
http://www.xilinx.com/bvdocs/packages/fg320.pdf

Schmartboard 202-0026-01 is BGA 400 Pins, 1.0 mm Pitch:
http://www.schmartboard.com/index.asp?page=products_bga&id=110

Diagram of 202-0026-01:
http://www.schmartboard.com/schmartboard_pd_202-0026-01.pdf

It would be benefitial if someone can clarify this matter. I have noticed this company in the past. Debunk time? :-D

[Darrin]

Xenepp wrote:
Another update, Dennis alerted me to V1.1 yesterday and I sent it off to China already.

Two weeks and thing will start to happen here! :-D

 -Joel

Good news.  You're the man!

Just out of interest, have you asked what it would cost them to actually produce an assembled board in various quantities?

I have all sorts of stuff in my house from when I worked in China and if they can assemble a complete set of Calloway golf clubs with travel bag for $170 then they should be able to produce an assembled minimig for a reasonable price.   ;-)

[tonyyeb]

Xenepp wrote:
Another update, Dennis alerted me to V1.1 yesterday and I sent it off to China already.

Two weeks and thing will start to happen here! :-D

 -Joel

Great news! Let me know when you want some cash.