@AmigaHope
I think you could MAYBE coax a DblPAL-type mode out of an OCS Agnus/ECS Denise system... You'd set the pixel clock for 35ns pixels and double the horizontal refresh
This is what would have to be done - but I'm not at all sure if Agnus buys it.
(I think Denise could force a horizontal blank without Agnus knowing about it)... and you'd keep the vertical blank the same.
The whole 'DMA' timing is based on horizontal scan lines and controlled by Agnus (it's no real DMA since chip RAM is Agnus local memory actually, the CPU is DMAing) - you might be able to trigger horizontal and even vertical blanking with Copper - but AFAIK it's questionable whether (old) Agnus resets to a new scan line as well.
I really have no idea if Agnus has to cooperate with Denise on horizontal blanks
Agnus is doing ALL memory access for chip DMA and passing the data to the appropriate targets (Dave Haynie has written some very enlightening info about this in the unfortunate '8 MB chip RAM in A4000' thread), so it's absolutely essential that Agnus knows about what to do.
(though I think you can free DMA time on the horiz. blanks so I guess there must be a capacity for Agnus to know about them).
I don't really get the point here.
Denise at its maximum doesn't eat up much in the way of the CPU's allocated chip mem bandwidth, but at that point any *OTHER* DMA you do (particularly with the blitter) starts seriously hogging the bus away from the CPU. By itself a 640x512x2bppx50Hz DblPAL screenmode eats just shy of 4 megabytes/sec of bandwidth. A1000/A500/A2000 chipset has roughly 3.5Mbytes/sec bandwidth dedicated to the chipset, and another 3.5Mbytes/sec that the CPU can use. You're not really stealing that much.
Running Hires/16 colors or SHires/4 colors uses ALL available chip RAM bandwidth during scan line (7 MB/s). The only access Copper, Blitter and CPU (in that order) get is during horizontal/vertical blanking (Paula and floppy are real time and have reserved time slots). If severe overscan is used, all operations slow to a crawl.
Once you start blitting stuff around a lot though, it eats up even more bandwidth and slows the graphics system down to a crawl (and basically kills the CPU if you have no FAST RAM). This is why CPUBlit-type patches speed up the system so much on high-bandwidth screens.
This goes double for A3000 ECS systems and AGA systems that give the CPU 32-bit paths to chip mem. Once you've eaten up the dedicated custom chip bandwidth, the blitter becomes a drag on the system rather than a benefit, as long as you have CPU cycles to spare.
But only if the CPU has 32 bit access to chip RAM (A3000/1200/4000) since even the AGA blitter works only on 16 bit at a time and actually wastes bandwidth. On A500/600/2000 systems you can't gain much, esp. w/o fast RAM.
Anyway the ECS 2-bitplane 35ns modes aren't so bad performance-wise, provided you have real fastmem and don't try to use the blitter. On the A3000 with its 32-bit chipmem they're actually VERY nice if you don't like the fringing motion effects that you get on deinterlaced screens.
Actually the A3k's chip RAM isn't 32 bit, only CPU access is. ;-) (It's got two banks and the CPU can access both banks simultaneously, somewhat like modern dual channel chipsets that can access two 64 bit channels as 128 bit.)
Of course, deinterlacing is a different problem, but on my A3k I've used NTSC interlaced (flicker reduced 60 Hz instead of PAL) much more than Productivity - before I bought my Merlin graphics card that is. :-D