Additional clockports for the A1200 ?

[mboehmer_e3b]

The A1200 revision 1A has two clockports and the extra port is located at P9A near the keyboard connector on the right

Wrong. Sorry. It is the normal expansion header for memory which was only present in early revision machines.
Don't even try to connect clockport devices there!

Please read the SUBWAY manual to get more information on this issue.

Michael

[CD32Freak]

Oops, sorry, thanks for this clarification ;-)

[leirbag28]

@joetee
"Perhaps you meant another HW product that fit over a PLCC chip?"

Joe....Precisly............There is a Device called the SilverSurfer Adaptor that plugs onto the Gayle chip in the A600. It gives it an A1200 compatible clockport.............I have this device and will be adding a Subway or Silver Surfer or Delphina Sound card soon.

 The adaptor I was refering to though was the Quaddddra port, which when plugged onto the Clockport of the A1200 or the (newly installed) clockport on the A600, it gives both machines 4 more clockports.  Neat eh? :-)

 I wish people would create more stuff like this.  Some of these guys are Brilliant!!!

[Stedy]

@sparky

The design you have, does it look like this?


I forgot I had this.

This required a connection to the Kickstart chip to provide the extra address decode needed.

I also found a picture of the original quadroport here: http://amiga.resource.cx/gallery/Quaddddroport.jpg

Bye

[Sparky]

Stedy wrote:
@sparky

The design you have, does it look like this?


I forgot I had this.

This required a connection to the Kickstart chip to provide the extra address decode needed.

I also found a picture of the original quadroport here: http://amiga.resource.cx/gallery/Quaddddroport.jpg

Bye

:-)

That looks pretty close to the description I got ... darn it  spoilt all the fun, but did answer a question I had :-)

Is this something you drew up ?  What are the implications of loading this up to Aminet ?

I'll still make some schematics up though as I can then get the PCB built quickly.

Thanks for that! :-)

[Stedy]

I did not draw it up, Daedalus/Robert Cranley did, see the title box!

I gave him some help and advice for the design a while back and had a copy in my posesssion. I would need to check with Daedalus if it can be released on Aminet, I will check IRC later on.

Be warned, the pinout is not as you would expect. Pin 22 of that schematic is pin 19 of P9B, pin 21, Pin 20 of P9B and so on (numbering from bottom to top).

Pin 37 of U6B is A14 and Pin 36 is A15. These decode a $4000 offset from $D80001, making the second two ports (CN3 and CN4)  appear at $D84001, the same as for a Quadroport.

This design would only accept 4 devices that need 8 address locations each.

While you are at it, design a version to fit over the 84 pin Gayle PLCC chip, then A600 users can join in!

Have fun,

Ian

[Stedy]

Hello,

The design I posted had a problem with the Interrupt handling, all the IRQ lines were tied together! So with 4 devices, if 1 signals an interrupt, it would fight the other 3 IRQ lines!

Also the original design does do the address decode for all the quadroports addresses, $D80000, D84000, $D88000 & $D8C000.

I redrew the schematic with the IRQ logic and put it here:
http://www.ianstedman.co.uk/Downloads/clockport_expander.png and as I had a bit of spare time, the PCB design is here:
http://www.ianstedman.co.uk/Downloads/clockport_expander-pcb.png
If anyone wants the Eagle CAD or Gerber files, I will put them online.

[platon42]

> The design I posted had a problem with the Interrupt handling, all the IRQ lines were tied together! So with 4 devices, if 1 signals an interrupt, it would fight the other 3 IRQ lines!

Is this really a problem? I thought the IRQ line (INT6) was tristate anyway.

[Doobrey]

@ Stedy..
 That`s freaky, almost spot on the same as the one I did a few months back.
 The only thing different on mine is that I used the other half of the 139 and the spare_cs as its enable, to drive the spare_cs lines on the 4 ports, just for completeness.

 I suppose it`d be just as easy to decode the Net_cs for one of the ports, AFAIK Gayle uses less wait states on accesses to that memory space..

[Stedy]

@Doobrey

Actually you just found my deliberate mistake!  :-D

I should have used _SPARE_CS not _RTC_CS for the address decode, that address space is taken up by the Real time clock in your accelerator! I will upload the revised schematic tomorrow.

To access NET_CS would require connecting to Gayle, which could be done but AFAIK, no software would support accesses in the decoded memory region.

So Doobrey, why did you not publish your design then?

@Platon42

Interrupts are never tri-state. If they were the CPU probably have un-defined operation unless external pull ups are used.

[Doobrey]

Deliberate mistake my ####  :lol:

 Wouldn`t the RTC on accelerator cards just take up the memory of the first port ?
 As for the Net_CS, I did have a few ideas..but getting hold of old ISA based ethernet chips with freely available docs is hard, although there is a company in the US that have a dev board that`ll just need an inverter on the interrupt line, and it`ll wire in fine.

 I will publish my stuff when I`ve finally tested it and got all the software working OK, which reminds me..
@Chris,
 Had any luck with the latest build I sent?

[Stedy]

@ Doobrey

Deliberate mistake my ####  

Ok, I made a mistake, now corrected (new drawing online).

Yes, the RTC should only take the first port of the RTC_CS area.

Take a look at Cirrus Logic, their CS8900 Ethernet chip, will work in an 8 bit ISA type mode. See AN181 'Using the CS8900A in 8 bit mode.'

Have fun!

[Doobrey]

I was looking for the CS8900 or the RTL8019 (I think it`s the 8019!..can`t remember without digging out the schematics),
 Just can`t find them in the UK in small quantities, Maplins used to do it, but they`ve cut right back on their semiconductor range. Couldn`t find them at Farnell or RS either.
 I might have to resort to buying an ISA card and getting out the blowtorch :flame:

 How`s your 24bit IO card coming along? Have you scrapped the clockport version to concentrate on the parralel port verion?

[Stedy]

@Doobrey,

For the CS8900, have you contacted
Unique Memec, UK distributors for Cirrus Logic parts?

Another option is SMSC, their 91C96, 91C100 and 91C111 will work with an 8 bit interface for the clockport.
Insight Memec distribute SMSC parts.

Both variants of my 24 bit I/O card have been built. I have tested the parallel port version and I designed a modified version for Xeron's CD1200 project. PCBs were made for the CD1200 board, not sure of current progress.

Details of both designs are on my website, with photos of the PCBs.

[Orjan]

Not strictly about the topic, but I opened my 1200 up, only to find that half the pins on the clockport were missing... Why is this? Are half the pins not in use?

[Doobrey]

You mean you have the rightmost 22pins on P9B ?
That is the clockport, all other pins were left over from the days when CBM were gonna make the A1200 with 1MB RAM, and sell an extra 1MB module that plugged into the P9A&B connectors.
 When they decided to make the A1200 a 2Mb machine, they simply didn`t bother soldering the pins to the unused holes to save money.
BTW, I`ve heard that some A1200s were built wrong, and had the 22pins meant for the clockport soldered to the leftmost side of the connector, if your A1200 is like that, dont plug anything into it, you could let out the magic blue smoke.