How L1 and L2 caches work

[biggun]

Edit: in the above examples I mentioned 20 cyles latency for 2nd Level cache
and in the performance calculations we used 10 cycle.

This is no error - but this was under the realistic assumption that the compiler can work around the latency sometimes a little, That a pipeline design can sometimes help and that Prefething or Out Of order can soften the penalty sometimes.

[psxphill]

@Biggun, sorry, I don't understand this,

An L1 cache is fast because it is small, make it bigger and it slows down, so they add an L2 cache, but an L2 cache is slower than an L1.
I do not understand why an L1+L2 is faster than a larger L1 cache.

Imagine you are looking for a nail in your garage and it's really untidy. You decide that you'll keep some nails in your toolbox that you keep by the door, but you can't fit them all in. As soon as you run out of nails in your toolbox you have to go back to finding them in your garage. Having a toolbox that is as large as your garage wouldn't help as you'll fill it with all type of crap again and it will take just as long to find it.
 
 

Even money an not change the law of physiscs.
And physics simply dictates that increased size needs more space.
More space means longer wires, Longer wires means longer lantency.
Its very simply physics - which everybody will understand.

They've hit hard limits before that were said to be impossible to break, until they were.
 I'm sure one day it will be cost effective to increase L1 cache, some funky 3d circuits or using light instead of electricity etc.

[A6000]

OK, Thanks for the replies.