Motorola has started transferring silicon-on-insulator (SOI) capability to the 90-nanometer manufacturing process technology being developed by the alliance of Motorola, Philips, STMicroelectronics and Taiwan Semiconductor Manufacturing Company Ltd. at Crolles, France.
From
http://www.siliconstrategies.com/story/OEG20030623S0089A PowerPC processor made for performance in 90-nm SOI CMOS, and for economic efficiency on 300-mm diameter wafers, should be in manufacture at Crolles in 2004, according to Claudine Simson, the recently appointed chief technology officer of the Semiconductor Products Sector of Motorola.
Work is underway at Motorola's Dan Noble Center in Austin, Texas, where the company is developing the 90-nanometer CMOS-on-SOI manufacturing process technology on the 200-mm diameter wafers that Motorola runs there in MOS-13 wafer fab. As that is perfected Motorola engineers are to transfer the high performance technology to 300-mm wafers being run at Crolles, Simson said.
Motorola engineers are in Crolles and SOI test chips for the 90-nm manufacturing process technology are expected to run on 300-mm wafers at Crolles, “this summer” Simson said in an interview with SBN (see June 23 story).
Of the technology transfer she said: “It's starting now. Test chips will run in Crolles in the summer and a PowerPC will run next year.” Simson said Motorola usually sees a 25 to 35 percent performance improvement for a given circuit over its equivalent in plain CMOS at the same minimum geometry.
In a keynote address to the Embedded Processor Forum last week Simson said Motorola is backing SOI to evolve from being a high-performance option to CMOS today to become the foundation of all leading-edge digital circuit manufacture over the next decade and several process technology generations (see June 19 story).
