A500 accelerators

[trekiej]

Does anyone know how an external accelerator synchronizes with the internals of an Amiga 500?

The accelerator goes 28mhz and the A500 goes 7 mhz.
Thanks in advance.

[TjLaZer]

Its not external, it connects via the Zorro bus.  It's just physically external.

[whiteb]

trekiej wrote:
Does anyone know how an external accelerator synchronizes with the internals of an Amiga 500?

The accelerator goes 28mhz and the A500 goes 7 mhz.
Thanks in advance.

Well, only one CPU can exist at a time, EITHER the External accelerator, or the Internal CPU.

If the External accelerator is present at boot time, then the 68000 will be sent into a sleep (HALT) state.  There is no physical way around this on the A500 (Any Amiga as far as i am aware)

Even the Phase 5 accelerator with 040/PPC on them, only one CPU will physically exist at any given time (AFAIK).

[trekiej]

What I have got so far is this.
For example a 68030 would send the 68000 a active Low BR.
Then the 68000 would send an active low BG. The 68030 gives an active low BGACK.
I feel the question now is how do two different clocks get synchronized.
I am suspecting C1, CDAC, C3, AS, and DTACK is responsible for  it.
Thanks.
edit:
humbly:I know that the 68000 does not get removed.

[trekiej]

Another example is when the 68000 is removed. I understand that there are wait states between buses with two different speeds. This may be the answer I am looking for.

[jj]

@ whiteb

Ummm the PPC cards from phase 5, do not send eiither proc into  a sleep state.  Both are running at the same time.

though OS4 does switch off the 68k proc