What determines the amount of usable ram on an Accel. Card?

[Miked]

Why is it that some old 030 accelerator cards (like the Viper 520, Mtec 020, A530+) can only address 8mb of Ram, while others can address 16, 32, 64, etc.  Is this a hardware limitation or a software limitation?  I guess what I am wondering is if it is possible to modify the amount of ram a card can normally hold?  (I suppose this would apply to cards that accept SIMMS)

-Miked

[Lemmink]

Accelarators that stop at 8 MB put it's RAM into the ZII autoconfig adressspace. This adresspace is simply 8 MB in size.
Accelerators that can handle more then 8 MB use an own memmorycontroller that adresses RAM in the 32bit adressspace outside of the autoconfig adresspace. Some controllers can hanlde 32 MB max. some 128 MB and some 256 MB.

[xeron]

As already said, cards that max out at 8Mb are usually putting their RAM into the 8Mb window of autoconfig space.

The A1200 motherboard itself has only 24bit addressing (its 68EC020 has only 24 address lines attached to it), and can only "see" 16Mb of memory. This is divided up into chip RAM, custom chip registers, autoconfig space etc.

Cards with more than 8Mb typically have a 32bit address bus (and an address space of 4Gb), or at least more than 24bits.

The lower 24bits are all connected to the A1200 address bus, and so the lower 16Mb of the address space maps to the A1200 address space. Anything above 16Mb can be divided up however the accelerator manufacturer likes.

The limitation on RAM in this case could be due to the number of address lines actually present on the card, the way the memory decode logic is configured, firmware limitations... it could be different for any given card since addresses outside of the A1200s memory range are decided by the card manufacturer.

Interestingly, this is why the A1200 mediator is somewhat crippled. Because it is not tied to any particular accelerator card, it can only use the 24bit addressing of the A1200, and therefore has only an 8Mb window which has to be mapped to one of many 8Mb chunks in the PCI address space. If the mediator had been done as an 060 card with a PCI bus on it (like the G-Rex), they would be able to address PCI cards properly without this limitation. Also, DMA direct to fast ram would have been possible. In short, it would have been much better, but presumably they did it that way because if people can use their existing accelerators, they'd be more likely to buy a mediator.

[Kronos]

A card that stops at 8MB might in the most cases put it's RAM in Z2-address-space, but thats true for all of them.

It's really a matter of how many address-lines are routed to the RAM-sockects, which is never the full 32, unless you've heard of a 4GB-PS/2-SIMM.

The numeber of lines is often defined by the RAM-standard of the time.

For example, all CybersStorms can only take 32MB per slot, while the BlizzardPPc will take 128MB.

Just because there were no modules bigger than 32MB defined at that time.

A (old) turbo design for 1MBit DRAM-chips might go to 4 maybe 8MB, adding more was impossible due to space restrictions.

A slightly never one might use 4MBit chips, costum SIMMs ZIPs... and will pack more onto the PCB.

[Kronos]

@Lemmink

Every card containing FAST-MEM needs to generate it's own refesh-signal (which is what a memory controller for DRAm does), it must also do it's own address-decoding.

Only CHIP and SLOW-MEM is refreshed by Agnus.

Cards above 24Bit aren't autocifiged by the HW, but must go the route via expansion to add their RAM to exec's list.

Either that or by a special "add-mem" command.

[Zac67]

Not entirely (though widely) correct: Z II autoconfig is limited to the noted 8 MB; in A3k/A4k there's Z III autoconfig space which allows for RAM cards up to 1 Gig, a total of 1.75 Gig Z3 memory. .25 Gig are reserved for fast slot accelerator cards.