Can you explain the chip ram DMA bandwidth issue? Or is there an easy link that would explain it?
Well, with the clock rate of the custom chips as low as it is, and the amount of data lines between the ram and the custom chips, there is a certain upper limit of how many bytes can be pushed out of the display at a time, and that limits the available resolution and the available number of bitplanes.
The OCS/ECS chip ram bandwidth saturates at 4 hires bitplanes, or (theoretically) at 8 lowres bitplanes. At that rate, the maximum amount of data theoretically possible goes from the RAM to the custom chips.
At that time, this was the highest achievable rate possible with state of the art technology.
Nothing can really fix that, within the limits of the ECS machine, this is as far as it gets.
If you want more colors, or higher resolution, get a graphics card.
CBM had a special monitor, the A2024, that also accepted refresh frequencies as low as 15Hz to enable higher resolutions. This monitor had an internal framebuffer to quadrupel the frequency from the system to the actual tube. There is some custom support in the Os to enable it - it requires a very specific chip setup to send an entire video frame in four iterations (four tiles) to the monitor.
The standard flicker fixer cannot do that. It can buffer a field (half a frame) to double the vertical frequency of interlace screens, but that's as far as its operation goes. It cannot interpret the special A2024 modes. (Which are really just a hack in the system).
