When looking at the trapdoor memory interface on an A500, I notice that there are back to back double writes happening to the RTC clock chip on the A501 module.
With the four-bit databus that is being used, I highly suspect that there's some BYTE to nibble conversion happening in Agnus/Gary.
For instance, the RTC address will stay the same, but the databus will first write "wrong" data or "0"-data, and then the second write containing the actual correct value.
You see a low-going pulse for /XCLKWR, then a delay (217ns?), and then another low-going pulse for /XCLKWR.
Note that this works absolutely fine in practice, but something goofy is going on. Unless there's some requirement that I can't find in the datasheet with the RTC chip to clear the value with "0" prior to writing it?
This is happening with each RTC register.
If I had access to the source code for the amigados "setclock" command, I could probably figure it out soon enough. I could disassemble it, but not sure how cryptic that would be.
Thanks
