A500 DRAM timing diagrams

[kamiga]

Hey all,

Would anyone happen to have, or know where I can find some A500 DRAM timing diagrams?  I'm interested in all the RAS/CAS/OE/WR stuff associated with the agnus to onboard memory and agnus to trapdoor A501 memory communication.

I looked through the service manuals and hardware reference manual.  I've seen diagrams for the 68000 side of Agnus, and some for the other custom chips..... but none that detail the DRAM memory controller.

Any chance that someone here successfully replaced say an A501 DRAM expansion memory with one based on SRAM?

Thanks

[GadgetUK]

Hey all,

Would anyone happen to have, or know where I can find some A500 DRAM timing diagrams?  I'm interested in all the RAS/CAS/OE/WR stuff associated with the agnus to onboard memory and agnus to trapdoor A501 memory communication.

I looked through the service manuals and hardware reference manual.  I've seen diagrams for the 68000 side of Agnus, and some for the other custom chips..... but none that detail the DRAM memory controller.

Any chance that someone here successfully replaced say an A501 DRAM expansion memory with one based on SRAM?

Thanks

No, but would be interested in that myself as I want to create a DRAM tester to test 41256 and 414256 DRAM chip from the A500, A500+, and ST using a PIC chip.

[kamiga]

No, but would be interested in that myself as I want to create a DRAM tester to test 41256 and 414256 DRAM chip from the A500, A500+, and ST using a PIC chip.

You can simply use the original branded datasheets to know how to drive those chips.... You should be able to do this fairly easily.  I could probably walk you through a high level overview of how to accomplish that if you're interested.  I'm crazy busy with this project right now, but if you'd find that helpful, I'd sit down and put something together.

Thanks

[Zac67]

Agnus' DRAM interface isn't suitable for SRAMs which have no multiplexed address bus. SRAMs can rather easily be interfaced to the CPU bus directly as FastRAM - just generate a CS and you're probably good to go.

[kamiga]

Agnus' DRAM interface isn't suitable for SRAMs which have no multiplexed address bus. SRAMs can rather easily be interfaced to the CPU bus directly as FastRAM - just generate a CS and you're probably good to go.

This doesn't sound like anything that a latch can't take care of, right?

Latch the row address when RAS goes low, latch (or just transparently pass-through) the column address (and WR?) whenever one of the CAS's drops.

The access time of a SRAM is much faster, and only has to beat the tCAC parameter (which is 60ns on the LH21256-12's or 75ns on 15's)

This requires some glue logic (a few inverters, and two flip flops in the current design, which is changing) to in essence "interface translate" the RASs/CASs into OutputEnable and ChipEnable's.  Configure the flip flops so that the chip is selected whenever we see as RAS-low then CAS-low..... which means that RAS only refreshes, or CAS then RAS refreshes don't accidentally select it.

The 256kx16's SRAMs have byte-level access that can be controlled by CASU/CASL.

There's definitely some gotchas, but it's coming along swimmingly.

[Zac67]

Of course it's possible. You just latch the high address part on _RAS and then use _CAS as _CS (more or less, there may be some tweaking required). But what's the point? It's easier to add it to the CPU side and faster as well.

SRAM doesn't require any refresh btw (and can't make any use of the cycle).