ACA card speeds

[Faerytale]

Those programs do not report the correct MIPS for 060.  They lie.  Forget about them.

Its dead easy to write a program that runs at 149 MIPS on 50Mhz 060.

The 060 has 2 integer cores so that is 100 MIPS right there.  Plus all predicted branches happen magically for free.  So that is 150 MIPS.

An 80Mhz 060 runs at 240 MIPS.

wikipedia SAYS:
Performance   ~88 Mips @ 66 MHz
                      ~110 Mips @ 75 MHz
                      ~36 MFlops @ 66 MHz

[ChaosLord]

wikipedia SAYS:
Performance   ~88 Mips @ 66 MHz
                      ~110 Mips @ 75 MHz
                      ~36 MFlops @ 66 MHz

FYI: Wikipedia lied.  But at least they had the decency to make up some new numbers. :lol:

Wikipedia also says that Wikipedia is never to be considered a reliable source of information and cannot be treated as an authority on any subject whatsoever.

[AmigaClassicRule]

FYI: Wikipedia lied. But at least they had the decency to make up some new numbers. :lol:
 
Wikipedia also says that Wikipedia is never to be considered a reliable source of information and cannot be treated as an authority on any subject whatsoever.

ChaosLord, if I pay you $60 dollars can you mail me a copy of Total Chaos in a CD with the LATEST VERSION EVER POSSIBLE and registered?

[psxphill]

FYI: Wikipedia lied. But at least they had the decency to make up some new numbers. :lol:
 
Wikipedia also says that Wikipedia is never to be considered a reliable source of information and cannot be treated as an authority on any subject whatsoever.

According to:
 
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MC68060
 
"The MC68EC060 offers superscalar integer performance of over 110 MIPS at 75 MHz".
 
In Motorola tests the secondary operand execution pipeline was used in 50% to 60% of instruction pairs.
 
Branch prediction isn't free when it takes the branch. It doesn't have a horrible penalty for flushing the pipeline when it guesses right, but it still counts as an instruction. Motorola claim over 90% success rate.
 
You can't get over 160mips at 80mhz and to even achieve that your code would have to fit into the 8k of cache, not do any moves from or to memory, it would have to perfectly predict every branch & your code would have to be very specialised to utilise both execution units on every instruction.

[bbond007]

FYI: Wikipedia lied.  But at least they had the decency to make up some new numbers. :lol:

Wikipedia also says that Wikipedia is never to be considered a reliable source of information and cannot be treated as an authority on any subject whatsoever.

wikipedia SAYS:
Performance   ~88 Mips @ 66 MHz
                      ~110 Mips @ 75 MHz
                      ~36 MFlops @ 66 MHz

my SysSpeed seems to be pretty close based on those wikepedia #s

I would project mine should be between 67 - 73 mips based the 66 and 75mhz numbers. 65 seems pretty close considering OS overhead which is few %

here is the math:

(88 * 50) / 66 = 66.67 mips (projected 50 mhz based on 66mhz)
(88 * 75) / 66 = 100 mips (projected 75 mhz based on 66mhz)
(110 * 50) / 75 = 73.33 mips (projected 50mhz based on 75mhz)

it seems like their 75mhz score may even be a little high

[ChaosLord]

"The MC68EC060 offers superscalar integer performance of over 110 MIPS at 75 MHz".
 

Ok, that is true.  Here is another true statement:

"The MC68EC060 offers superscalar integer performance of over 3 MIPS at 75 MHz".

Branch prediction isn't free when it takes the branch.

Maybe you are mixing up the 040 or something.

On the 060 a correctly predicted branch is free when it takes the branch.

Another way of saying it is:
Correctly predicted taken branches take 0 cycles to execute.

Another way of saying it is:
Branch-folding.

Another way of saying it is:
Awesome!

You can't get over 160mips at 80mhz

 Yes you can get 240 MIPS at 80Mhz.  It doesn't require black magic or sacrificing virgins or carving pumpkins or anything.

 and to even achieve that your code would have to fit into the 8k of cache,

That is not hard at all.  8K is a huge amount of code for a single loop.  This isn't an Intel or PPC processor.

All Amiga MIPS testers I have ever seen, even the fake ones, fit into less than 256 bytes or  0.25k.

 not do any moves from or to memory,

Of course you can do moves to and/or from memory.  The 060 has this magical box called "The L1 Cache" which caches all reads and writes for spectacular performance.  L1 Cache is massively more powerful than L2 or L3 caches which I guess is what is confusing you.

MIPS tests do not test memory speed anyway so it does not even matter.  All a MIPS test does is measure CPU speed.  Use a memory tester to measure memory speed.

 it would have to perfectly predict every branch

That is not hard to do in a timing test loop.

I have looked at the code for various timing tests on the Amiga that were written long before 060 existed and all their branches end up as correctly predicted as taken.  In other words the 060 came out later and did all their branches at 0 cycles per branch.

 & your code would have to be very specialised to utilise both execution units on every instruction.

All MIPS tests are "very specialised" to start out with so this statement doesn't mean a whole lot.

I mean you can write code ON PURPOSE not to dual-execute as that so-called Amiga MIPS tester proggy does.

Or you can use your brain and write code that does dual-execute.

If a MIPS-tester can't dual-execute then it isn't testing your CPU.  Your 2nd core could be completely broken and you would never know, because that pretend fake MIPS tester wasn't actually testing the 2nd core.

[Britelite]

The 060 has 2 integer cores so that is 100 MIPS right there.

Not all instructions are 1 cycle and not all of them can run in parallel. So yes, in theory you can get 100MIPS, but in real use you don't.

[Britelite]

Of course you can do moves to and/or from memory.  The 060 has this magical box called "The L1 Cache" which caches all reads and writes for spectacular performance.

Yes, if you only happen to be reading from cache, but once you get a cache miss the whole memorybus stalls for a number of cycles.

If a MIPS-tester can't dual-execute then it isn't testing your CPU.  Your 2nd core could be completely broken and you would never know, because that pretend fake MIPS tester wasn't actually testing the 2nd core.

There's not two cores as such, there is the primary and the secondary pipeline. And some of the instructions can only run in the primary pipeline, and even block other instructions from executing in the secondary pipeline.