let's dream about the mini-minimig for a bit...

[downix]

Not that dissimilar to my own design, save I have a 2.5" IDE connector on the mobo.

[Lorraine]

/

[persia]

Why would people want an hard drive on a mini-mig?  A 32 GB SD card would hold everything you could possibly want and at class six would be much faster...

[downix]

Lorraine wrote:

downix wrote:
Not that dissimilar to my own design, save I have a 2.5" IDE connector on the mobo.

Have you got a Laptop drive instead of flash, or is it used for something else?

Still have my old A1200 hard drive actually.

[asymetrix]

I looked in youTube for reflow toaster and bga rework.

http://uk.youtube.com/watch?v=0OIMmQkAuDQ
http://uk.youtube.com/watch?v=w1pxKN4UAXg

The method they use is either a hot air station or
use T962 Infrared SMD & BGA IC Automatic Reflow Oven from http://stores.ebay.co.uk/ACCUNI-EXPRESS

Which method is best ?

I think we should setup a bounty for a REFLOW station for Amiga projects

[persia]

An "Amiga in a Joystick" would be neat.

[alexh]

FrenchShark wrote:
We should move to Altera FPGAs.

Not used them for a while (3 years) but the Altera FPGA tools always sucked ass. The Xilinx ones being based on Synopsys were always better. Things changed recently?

Start using complex generate statements, non integer generics, arrays of pointers of enumerated types etc. and Altera tools blew up.

But if that is the largest Xilinx QFP then I guess to keep it home-brew capable then a switch might be inevitable.

[freqmax]

alexh:
How is Actel tools (libero?) in regards to complex statements?

One could also skip the onboard MCU and replace it with another XC3S500E FPGA + eeprom. That way fpga0 can boot from eeprom, and load fpga1 with flashmemory files. And then fpga1 can reset and load fpga0 with next set of files from flashmemory.

That way we get larger FPGA grid, and rid of one chip. Possible the m68k can be softcore aswell this way.

Btw..
"Synopsys and Microsoft Work Together to Improve Electronic Design Productivity" (abandon all hope )
http://www.ng2000.com/fw.php?tp=electronic-design

[FrenchShark]

freqmax wrote:
One could also skip the onboard MCU and replace it with another XC3S500E FPGA + eeprom. That way fpga0 can boot from eeprom, and load fpga1 with flashmemory files. And then fpga1 can reset and load fpga0 with next set of files from flashmemory.

Altera FPGAs have chipselect pins for configuration, with some extra I/Os on the PIC, you can get them configured one after another.
The problem with multi-FPGA design is that you need a communication bus between them that consumes I/Os...
The best solution I have found so far is to put a FlexBus bus (see the Coldfire MC548x). It consumes "only" 44 I/Os (28 if we use DDR on some signals).

With a 3-FPGA design (2 x EP3C16Q240 + 1 x EP3C10E144), you have enough I/Os to implement an Amiga AGA clone with all the legacy peripherals plus USB (ULPI interface) and Ethernet (MII interface).
It is quite costly : ~$80 for the FPGAs. Anyway, a medium sized BGA FPGA is not cheap either.

Regards,

Frederic

[FrenchShark]

alexh wrote:

FrenchShark wrote:
We should move to Altera FPGAs.

Not used them for a while (3 years) but the Altera FPGA tools always sucked ass. The Xilinx ones being based on Synopsys were always better. Things changed recently?

Start using complex generate statements, non integer generics, arrays of pointers of enumerated types etc. and Altera tools blew up.

I am not a big VHDL guru. I do not use variables so much, I use a little bit of generate statements to reduce VHDL source size, I also use type definition for state machines and arrays. I have never used pointers in VHDL (what kind of crazy design did you work on ?:-o)

I have found few bugs on Altera tools. I was able to work around them so far.
I remember that in 2005, Quartus II was quite unstable. Now, it is a lot better.

Regards,

Frederic

[freqmax]

An fpga-fpga internal expansion bus serialisation of 8 MHz, 16 bit data, 24 bit address gives a 3072 Mbps datarate. The XC3S500E manages 500 Mbps LVDS. So it doesn't need that many I/O ports.
And there's proberbly room for optimisations.

And yes dual fpga will consume I/O, but will also gain a lot more I/O than lost.

You can load all FPGAs from a single eeprom but the catch is that changing core will be a pain for non developers. That's why my preference for an flashmemory load.

Using MS-win kills the possibility for efficient remote console. Requires local harddisc. And gives the headache of virus etc..

[FrenchShark]

freqmax wrote:
An fpga-fpga internal expansion bus serialisation of 8 MHz, 16 bit data, 24 bit address gives a 3072 Mbps datarate. The XC3S500E manages 500 Mbps LVDS. So it doesn't need that many I/O ports.
And there's proberbly room for optimisations.

If I put a FlexBus is to make it run at 57 MHz or 114 MHz :-D

And yes dual fpga will consume I/O, but will also gain a lot more I/O than lost.

Agree, in this case, one Cyclone III has 160 I/Os, two will have 232 I/Os, maybe 264 I/Os if I use DDR.

You can load all FPGAs from a single eeprom but the catch is that changing core will be a pain for non developers. That's why my preference for an flashmemory load.

Using MS-win kills the possibility for efficient remote console. Requires local harddisc. And gives the headache of virus etc..

The PIC solution is kind of neat but little bit slow. I would prefer putting a SX-28/48 or even a Propeller.
For developers, the best is still JTAG : immediate loading and easy debugging.

Regards,

Frederic

[freqmax]

I defenitly agree on JTAG for development. Still the MCU function is mostly auxillary support so it should be kept at a low cost.
Also in a dual FPGA solution one could implement a flashmemory loader. And this could perform more or less at the very limit of physical components unlike any CPU.