To be honest I dont quite have the knowledge of the relationship between 680x0 CPU cycles (i.e. 50MHz 20ns) and 680x0 Bus cycles, especially when you start to include RAM pre-charge & burst access not to mention synchronous and asynchronous access.
If you look at some of the performance figures of 50Mbyte/s that most 50MHz Amiga 060 cards had it equates to 4 cycles per access. (4 cycles = 80ns)
If you look at the performance figures for the Centurbo they also average 4 cycles per access. However 4 cycles at 100MHz is 40ns, beyond the capability of SIMMS.