Adapteva Parallella-16

[nicholas]

If I understand this correctly it is to ARM what the Cell Broadband Engine is to PPC?

[nicholas]

it's a very fascinating design because these are all separate CPU cores rather than vector units, which has the potential of opening up different use cases.

Oh that's quite different than the Cell and more akin to the traditional multicore SMP model if each of these cores is just a standard ARM CPU.

I'd like to see how a heavily multithreaded API/OS design like the BeOS would scale on one of these things.

If only I had the talent.

[nicholas]

They are *not* ARM CPU's.

It's their own RISC architecture. Very simple design. Slightly super-scalar (it can execute one full integer instruction and one full floating point instruction per clock cycle, and looks like some degree of pipelining. It has 64 general purpose 32-bit registers. The instruction set is from what I can see quite a bit smaller than M68k but powerful enough.

They are definitively fully general purpose CPUs. You could run a "real" (non-MMU) OS on one with enough porting effort (though the low amount of per-core memory would make that very wasteful)



I think trying to port a general purpose OS directly to the Epiphany architecture won't make much sense at this stage. It might be fun to do if/when they meet their goals of versions with substantially more per-core memory.

Something more esoteric, like a FORTH based micro-kernel might be fun and very much doable, though

Speaking of esoteric Forth implementations, this one is pretty impressive.

http://jupiterace.proboards.com/index.cgi?board=otherforth&action=display&thread=204