@theguru
You're asking for a gague that is impossible for a layman to understand.
For example, my Eddas chip is 80% done by one measurement ( total workload), 60% done by another measurement (total files completed) and only 30% done by another (total gate density of final compile). I can go around saying 80%, and it would be right. I can also go by 60%, and also be right. Or by 30% and STILL be right.
So how do we measure? I mean, the remaining 20% work estimate might baloon because of some problem with the design that I'd overlooked. Or I finish it, then find a patent that infringes, so I have to rip it out and re-do it again. It's a fustrating process.
