PPC Developers Board

[downix]

I theory yes.  Actually a good basis to work from, if you had the schematics for it.

[downix]

HenryCase wrote:

This would just be the first step towards PPC Minimigs, but an important step IMO. Downix, your Minimig accelerator slot project is also key here, how have things been going?

Schematics are done, it's the pcb that I am slow at.  (never been fast at pcb's sad to say)  Would you like me to post the schematics as/is so as to see what I am attempting to do?

[downix]

itix wrote:

603PPC, 060 processor

Are those CPUs available anymore?

Yes, 060's come at up to 100Mhz now, and 603e's can reach 300Mhz.

Incidentally, I have a bus interface module designed for the 750-series as well.  Was going to use it in Eddas back when I flirted with using a PPC (too many headaches for me), but glad to donate it if you'd like.

[downix]

kolla wrote:

Yes, 060's come at up to 100Mhz now

You have reference for this, other than slightly vapored CT60?

Freescale certainly has no clue about this, they sell full 060 at 50MHz and 60MHz, and have LC (broken FPU) and EC (broken FPU and MMU) available up to 75MHz.

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MC68060

Have a dishwasher with a 68EC060 that runs at 100Mhz, didn't look to see if a) it's overclocked or b) if it was available in normal 060's.  My appologies, what I said, retracted.

[downix]

HenryCase wrote:

downix wrote:
Incidentally, I have a bus interface module designed for the 750-series as well. Was going to use it in Eddas back when I flirted with using a PPC (too many headaches for me), but glad to donate it if you'd like.

Should be useful for future developments, and any PPC information is very welcome, I have a lot of learning ahead of me. Thanks downix.

I'll dig it out  It is based on the Xilinx reference design for the Virtex 2, so it will likely need to be adapted to a new source

Eddas, what's that?

Enhanced Direct Data Acceleration System, a chipset I've been tinkering with since '97.  By tinkering I mean writing specs, doing some coding, finding that I made a judgement error, go back to specs, recode, retest... At present it's a SPARC based IO Processor w/ DSP accelerator tied to a a video display system and audio engine.  Never likely will finish it, no time to finish development, and the target keeps moving.

[downix]

HenryCase wrote:

downix wrote:
I'll dig it out It is based on the Xilinx reference design for the Virtex 2, so it will likely need to be adapted to a new source

Thanks downix. Please contact AJCopland if you need help with hosting the information.

Have my own host, thankfully, just need to get off my butt and get it all together

downix wrote:
Enhanced Direct Data Acceleration System, a chipset I've been tinkering with since '97.

Sounds interesting. From your description it sounds like a configurable input device platform which also handles video and audio processing. Is that right? How do you envision the chipset being used, what improvements would it bring to a system (if it was finished)?

Rather than stcking to old standards, which eat up silicon and slow down the system, it is a whole-cloth design change.  The video display system, for instance, can generate a windowing GUI in a fraction of the RAM than a vga-based display system, and context switching or even resolution switching is also much simpler.  

The basic concept is, rather than add modern features such as memory control, DMA, and bus mastering to an older (XT) based system, you build it from the ground up around these concepts.  You get a performance boost for general functionality and can grow the system with less conflicts as well.  In addition, it is flexible in nature, so rather than having a massve GPU that sits idle while you crunch spreadsheets, you have a massive DSP which can run your spreadsheet, or as a GPU for when you run that must-have game.  I'm in the middle of re-designing this DSP to avoid several patents I ran across.

[downix]

HenryCase wrote:

downix wrote:
Rather than stcking to old standards, which eat up silicon and slow down the system, it is a whole-cloth design change.  The video display system, for instance, can generate a windowing GUI in a fraction of the RAM than a vga-based display system, and context switching or even resolution switching is also much simpler.  

I have no idea how you are achieving this, but well done anyway!

Well, for example, the classic RAMDAC model, where your GPU, once you've finished rendering the 3D scene, NOW has to put the frame together.  I split this function away from the 3D section, slimming both cores while being more flexible.  Also I focused a lot more attention on memory control and bus utilization, two areas that really lack in normal PC's but are focused on heavily in the heavy duty workstation market.

downix wrote:
The basic concept is, rather than add modern features such as memory control, DMA, and bus mastering to an older (XT) based system, you build it from the ground up around these concepts.  You get a performance boost for general functionality and can grow the system with less conflicts as well.  In addition, it is flexible in nature, so rather than having a massve GPU that sits idle while you crunch spreadsheets, you have a massive DSP which can run your spreadsheet, or as a GPU for when you run that must-have game.  I'm in the middle of re-designing this DSP to avoid several patents I ran across.

Could you achieve a similar result by designing a hardware template that included a Tesla GPU as standard, running an OS built using CUDA? More info here:
http://www.nvidia.com/object/tesla_computing_solutions.html

Tesla is unable to be purchased without the display engine nor the memory control system, so would be wasting a lot of silicon for no gain.  Conversely, I could utilize an Ageia Phys-X as a GPU much more efficiently, for this reason.