MiniMig + PowerPC = OS4 Hardware for all

[downix]

HenryCase wrote:

Finally, read the last paragraph of the first post here:
http://www.power.org/forums/viewtopic.php?t=712
Free SPARC and MIPS clones of PPC chips exist! Tried to find them, no luck so far, but I would imagine it's a cheaper solution than the Virtex-4 one. If we made our own SPARC or MIPS core we could even integrate the MiniMig (complete with 68K CPU processes) into one chip capable of running OS4, given enough time.

No, that's not what he said.  He said that free clones of SPARC and MIPS CPU's exist.  You can find both on the opencores.org website.  SPARC is an open standard, Sun even released the code to their high-end UltraSPARC T1.  MIPS, however, is not, and true clones are liable for lawsuit due to patents.  Same with PowerPC.

[downix]

HenryCase wrote:

downix wrote:
No, that's not what he said.  He said that free clones of SPARC and MIPS CPU's exist.  You can find both on the opencores.org website.  SPARC is an open standard, Sun even released the code to their high-end UltraSPARC T1.  MIPS, however, is not, and true clones are liable for lawsuit due to patents.  Same with PowerPC.

Damn. Well, thanks for clearing this up for me downix.

Slightly OT, I was looking around the opencores.org website yesterday, came across this device:
http://www.opencores.org/projects.cgi/web/usbhostslave/overview
If the 68k core is integrated into the MiniMig FPGA, freeing up enough I/O capacity, this seems like a cheap way of adding the much requested USB functionality to the MiniMig. Of course we'd have to write our own drivers for it.

Incidentally, wouldn't there be legal repercussions if the 68k chip was emulated in FPGA form? And could we be sued by the A500 custom chip patent holders (I doubt OCS is open source)?

Unless you have a beefy CPU (like a 25Mhz 68030) then USB would still bog you down.  Now, that being said, if you could expand the MiniMig's RAM, you could add an embedded controller for it, and handle it like a firewire for data transfers, and like PS/2 for mouse/keyboard, but then you'd need a bigger FPGA.  I've used that core in a few projects, never had an issue with it.

The OCS patents expired a few years back.

[downix]

mdwh2 wrote:

AndrewBell wrote:
Even if it isn't demanded, you can run OS4 on AGA. Besides that, look at the bigger picture. Clone-A and Minimig, if available on PCI cards, offer Amiga graphics facilities to modern, fast CPUs. They still have features that are not present on modern 3D accelerated gfx cards, such as sprites, collision detection, playfields, hardware scrolling etc. Jens has even talked about extending the capabilities of the chipset.

Surely all of these things can be reproduced on modern hardware? Sprites can be done in hardware, certainly. Scrolling can be done with texture mapping, and would be at least as fast as the Amiga's hardware scrolling, surely.

if you brute force it, maybe.  But remember, it takes a multi-Ghz CPU to emulate a cycle-inaccurate version of the chipset as/is.  To make it a true clone, you'd be pushing multiple multi-core CPU's just to handle the chipset.

The Amiga's blitter alone is incredibly difficult to copy in simulation.  It's design is more akin to an ancient Crey than it is to traditional hardware, resulting in a huge overhead to make it accurate.  When you look at the cost, a pair of $1400 CPU's or a $35 FPGA... which is the cost efficient method?

[downix]

HenryCase wrote:
Been having some more thoughts on how to do this Minimig+PPC solution for new OS4 h/w. I'm trying to work out the different ways Amigas were able to be upgraded with fast co-processors. Considering the Minimig is currently A500 compatible (mostly), I have focused on the A500/A2000 solutions. I have a few questions:

1. Which one of the custom chips in the A500 controlled access to the side expansion slot?

CPU-driven only.  I've been working on a modified MiniMig to give it a similar expantion capability

2. On the A2000, what chip was mainly responsible for control of the CPU fast slot (as far as I can tell it is likely to be either the Buster, Paula or Gary OCS chips)?

CPU, again

3. How did the A2000 handle having so many expansion slots at once? Did it have a chip that switched between Zorro slots for instance, or were all devices running simultaneously?

they were running simul, but switched access to the memory bus.  Buster drove these

4. Of all the connectors/ports/sockets found on this list (http://www.amiga-hardware.com/connlist.cgi), which is likely to be the easiest to implement (not counting the connections the Minimig already has)?

A500 CPU-style slot

The question that is causing most confusion for me is question 3. The A500 side expansion slot is 86pin, the A2000 CPU Fast Slot is 86pin, and I can't find a OCS chip that has enough pins to deal with either (Buster OCS is 50pin, Paula OCS is 48pin and Gary OCS is 48pin). How was it done? How do PCs do it (something to do with the Northbridge/Southbridge combo AFAIK)?

Thanks in advance.

The CPU slots were just that, CPU slots.  They were directly off of the main CPU bus.

[downix]

HenryCase wrote:
Thanks for your reply downix, helpful as always.

I'm glad to hear you're working on a modified Minimig that gives it A500-like expansion capability. It would be a great leap forward for the future of the Minimig if this can be achieved.

So the CPU drives the main CPU bus, makes sense. However, I still don't quite understand how it was done. The A500 used a 68000 processor, most of which are 64pin (there are some 68pin variants out there). How did a 64pin chip interface with a 86pin expansion slot? Seems to me that the only way would be to send the information in serial rather than parallel. If the information was sent serially, how many pins of the CPU did the expansion slot need for communication?

Thanks again.

Power, some timing signals.

I made an adaptor once, for instance, that put a thin PSU into a side expantion, getting rid of my brick.  You can power the whole board through the slot if you so desired.  But it's still pretty much just direct access to the CPU bus.

My own design, mind you, is technically the same bus, but at 3.3v rather than 5v.  That way you could add 5v should you desire using a basic adaptor, or use more modern 3.3v peripherals instead.