MiniMig + PowerPC = OS4 Hardware for all

[downix]

Hans_ wrote:

AFAIK, PowerPC is licenseable as well. IBM and Freescale own it (I think that IBM may have more say), AMCC and PASemi are licensed to use it, as is Xilinx, for their Virtex-4 FPGAs. I have no idea what the licensing costs are.

In the end, the actual CPU won't matter too much. The old OS will be sandboxed either way. So long as we make the jump to 64-bit, it's all good. However, a 64-bit PowerPC CPU would make the transition easier as there's no emulator to write. Forget buying PowerPC chips from Freescale; there are other vendors with better implementations.

Hans

And still no northbridges nor ones with integrated modern northbridges.  I looked into licensing the PowerPC, with no luck.  I also looked at Coldfire licensing, no go.  You can make a clone, as some folk have done, but if you're doing that, might as well clone the 68k directly.

At this time, SPARC remains the best choice, in my opinion, for a next-generation platform.

[downix]

HenryCase wrote:

downix wrote:
SPARC, ARM or SuperH would be my recommendation (in that order)

Reading your other posts downix, I do like the sound of SPARC. I know it's not the correct measurement of speed, but what's the fastest SPARC CPU out there clock cycles wise? This looks awesome...http://www.sparc.org/news/07aug7.01.html

SuperH sounds pretty good too (http://en.wikipedia.org/wiki/SuperH). What would be the advantages/disadvantages of this architecture compared with the other ones examined in this thread?

The T2 is technically the fastest SPARC but it does it through massive parallellism.  16 ALU's is a lot of horsepower, blowing away even the best Xeon or Opteron on the market.  However, core-wise, the Fuji SPARC64 IV is actually the fastest.  However, the SPARC64 IV does not allow for the parallellism that the T2 does, so it comes down to how parallell your operations are.  Massively threaded, the T2 is the fastest.  Single operations, the SPARC64 IV is.  Also, unlike the x86, SPARC is designed around the concept of load-balancing co-processors, able to remove tasks from the system bus, not overloading the CPU with dumb tasks which will bog it down.  Can't avoid that in x86 architecture easily, I've tried.

SuperH is a very good mix of technology, coming in dead between the MIPS and ARM for performance/scalability.  I still have not gotten good information about licensing, but it seems approachable.  

[downix]

freqmax wrote:
@downix:
motorola/x86/etc.. whichever way I think the point is to take the best
technology below the price bar for most people and apply it in a clever way.
That's what commodore did. Any m68k/PPC is plain nostalgia or for embedded
development not cutting edge.
Even if you don't like non-free cpus they may work as a temporary solution
in the meantime to let one concentrate on other issues.

Even for price/performance, m68k, coldfire and PPC are below the curve.  You'd still do better with a MIPS or ARM CPU anyday.

But you have to start on the hardware first, else you don't have a leg to stand on.  The best software is worthless without a machine to run it on.

[downix]

freqmax wrote:
@downix:
"remove tasks from the system bus, not overloading the CPU with dumb tasks which will bog it down. Can't avoid that in x86 architecture easily, I've tried."

Could you explain in more detail ..?

As for hardware my point was that one can build hardware and use a off the shelf cpu. And build software for that solution. Later on one can replace the cpu, because most code is high level and not assembler. Thus the only needed replacement is the compiler.

Well, basically it comes down to how a system handles OPS.  In the m68k's case, it only utilized the memory bus in such a way that a) you could add registers to the setup without having to remap the whole bloody thing, and b) you could have a parallel set of instructions being fed to another processor.  In the Amiga's case, the Copper was being fed those instructions.  In the old Sun 680x0-based machines, it utilized a series of I/O co-processors which handled networking, disk tasks, and other low-level tasks.  Sun, when they decided on making their own CPU's, kept this capability, allowing for their new SPARC CPU to "drop-in" hardware-wise with their older m68k's.  PowerPC however is based on a CPU-centric design, the IBM POWER, whereby all register maps, OPS, etc have to be handled by the central processor, same as Intel's 8086, the ancient ancestor of modern day PC's.  It makes sense for a mainframe, which does not have heavy IO tasks beyond the disk access.  Other companies that also used the m68k, such as HP and SGI, wound up with similar solutions to the SPARC, the PA-RISC and MIPS respectfully, and also are designed to allow for co-processing with a minimal amount of glue logic and OS overhead.

Think on it for a minute.  Every time you make a call to that GPU within your desktop, the instruction first has to go to the Intel or AMD CPU, which then goes "a ha, this isn't mine, it goes to device 0, just a moment."  Adds a lot of overhead to the design.  And yes, this is overly simplistic, but the general concept is the same.

Incidentally, SPARC's do allow for off-the-shelf CPU's.  Sun and Fujitsu both supply SPARC CPU's to 3rd party vendors, ranging anywhere from the 650Mhz UltraSPARC IIi to the SPARC64 IV.

[downix]

little wrote:
I think a custom CPU core or an efficient but little know CPU are a dead end in itself. Either you are a trailblazer or a follower, you cannot be both. If the people in this project are so sure to make something so good they will set a trend, attract programmers and have long lasting weight in the market then go ahead. If the idea is to use what at this moment seems cutting edge from other companies remember it becomes old tech in six month old. Like in the example downix gives, MIPS was the best choice at the time and Sony used it and made a trend because the PSX was a trailblazer. Nowadays MIPS is barely a memory and for quite some time sony has not used that architecture in anything new.

That eliminates Coldfire and m68k right there.  Right now, SPARC, ARM and a case could even be made for PowerPC as the have-to-have CPU's.  And as of right now, SPARC remains the best for the budget, and now offers the fastest CPU on the market for parallel tasks, the new UltraSPARC T2.  Incidentally, Sony still uses the MIPS CPU in their PSP handheld.

[downix]

HenryCase wrote:

freqmax wrote:
@HenryCase:
Don't wake the patent bear
Amiga was not only the custom chips, but also how things were wired together
on a system level. And software to go with it that was efficient.

The patent bear has already been woken, I e-mailed DCE earlier tonight. I'm only asking for information at the moment. In any case, Yogi is my lawyer, and he's smarter than the average bear.  :roll: :-D

I agree that the whole system needs to be well thought through, but thought I'd mention the custom chip thing just in case we forgot that was an important part of the identity of Amiga hardware. Maybe we should think about DSP options too, like the final Commodore Amiga h/w designs (i.e. the ones that never made it).

downix wrote:
*Lots about SPARC*

Downix, the more you say about SPARC, the more I can see it as the absolute best solution we have for moving the Amiga platform forward. If a version of AmigaOS or AROS could be made for it (even without support for the multithreading at first), then it would be a brilliant step in the right direction. The parallel processing part would take a long time to implement, but would be worth it in the end. Are SPARC CPUs expensive?

A basic entry-level can be had for less than $20, a server-grade unit for over $1000.  I picked up my UltraSPARC IIi system for $50 used, and while it lacks the multithreading support of the T1, it is a good development platform.

[downix]

HenryCase wrote:

downix wrote:
A basic entry-level can be had for less than $20, a server-grade unit for over $1000.  I picked up my UltraSPARC IIi system for $50 used, and while it lacks the multithreading support of the T1, it is a good development platform.

 :-o

That. Is. Unbelievable.

Seriously, if making the switch was an easy process, this would be the architecture I'd pick. I'm sure there are other equally impressive CPU architectures out there, but SPARC has the right price, power, availability and suitability for next-gen Amigas.

However, in reality I would rather Amiga Inc didn't touch it, simply because they can't seem to get anything out to sell us. Let them finish that ACK design and get it out to us, then we should be in discussion with them about the future. Unless AROS could be made to run on SPARC architecture, then we'd really be in business.  :-D

It already runs hosted.  Getting it native should not be too difficult now that AROS handles 64-bit.

But yes, forget AInc, let us focus on a corporate-legacy free future.  

*edit*
here's an example of the machine I just bought:
Here's one
They're not highly prized as far as Sun's go, due to the CPU-driven IDE bus which does hurt system performance, but for a development machine, it's a solid 64-bit SPARC.  Incidentally, it's CPU is a IIi, not a III.
Another collection
And another one...
Not bad for 5 minutes on ebay.  I just type in Sun Ultra and here they are.

[downix]

AJCopland wrote:

little wrote:
Nowadays MIPS is barely a memory and for quite some time sony has not used that architecture in anything new.

...except for the PSP which is MIPS32 based with matrix/vector co-processing hardware. Oh and the PS2. Mips is quite a nice architecture to work with actually. Not the best but nice and simple to get used to I found.

Andy

EDIT: darned typos...

The original PS3 had a MIPS chip in there as well IIRC.  Not as the main CPU, mind you, but in a peripheral fashion.

[downix]

freqmax wrote:
@downix:
"add registers to the setup without having to remap" what do you mean by remap?
How does these custom "cpus" know when to run or halt?

Well, if I insert a bank of registers, it has to fit somewhere into the memory map of the system.  But, 8086 dictates a lot about where you are allowed to map these banks into a system, how many you can have, the size, etc.  To work around it is a headache.
And typically custom co-processors are started by the main CPU, and flag when they're finished through an interrupt.  But, in some cases, they can keep going, fetching the next set of work without needing CPU guidence, through a dedicated co-processing element such as a dedicated "stack-start" register, or other methods.  Lots of ways you can do it.

and @Crumb
Just looks like AROS on Linux, but I can grab a shot for you in a bit once I recompile it.

[downix]

little wrote:

A basic (SPARC CPU) entry-level can be had for less than $20

What about giving the name of this CPU so a real comparision between this and other CPUs in the same price level can be achieved?

BTW, The PSP is basically a scaled down version of the PS2, which was launched in 2000, in computer years that is a lifetime ago :-P

That would be the one I mentioned earlier, the S1.  It's a bit too new for real detail on specs, but as the core is similar to the UltraSPARC II, I'd compare it to that.  Which does mean that it's performance is comparable with, say an AMD Athlon 800Mhz, but while consuming 1/5th the wattage.  A lot faster than the SoC PowerPC's we're currently looking at.
In addition, there is also the MicroSPARC, which retails for $15, but it is a 32-bit SPARC, not a 64-bit, so not a very good comparison.  Also the PicoSPARC, same issue.  The Geisler LeonSPARC can also be had for this price, but again, 32-bits.  The S1 and II are the two entry-level 64-bit CPU's at this time.  I don't know Sun's pricing on the II atm.

[downix]

@downix:
What do you mean by "bank of registers" ..?

In the case of Amiga (or even Sun). The co-cpus are started by the main cpu and then continue until told to stop?, or do they start at system boot directly (like the main cpu) ..?

Well, in some setups (like the Amigas) registers can be mapped just like memory, so I typically call them the same way I would a memory bank.
And no, the CPU starts to co-pro (hence why it's a co-pro and not a full processor).  How it starts them depends on the CPU and co-pro.  In the Amiga's case, the CPU just had to write the starting address to the coppers control register, and that started it running.

[downix]

AJCopland wrote:

So the real question is: Is it possible to do a basic PPC board with soldered on (DDR?) SD-RAM, the FGPA (500k gates+) and the MiniMigs current connectors for less than £200?
Andy

Not realistically, no.

[downix]

AJCopland wrote:

downix wrote:
Not realistically, no.

:lol: well its good to get that out of the way at least! How come though? I realise that the examples I'm thinking of are commercial ones like the LinkStation or some set-top boxes, I guess they have ecomony of scale on their side.

How about the boards for PPC then? Is it feasible for us to do homebrew boards with only two layers that support a PPC chip or are they going to require more as a minimum? I ask since it gets more expensive for people to make N-layer boards doesn't it and anymore than two is instantly outside the scope of etching our own.

The sheer number of pins and the short distances that they can run makes 2-layers very difficult to manage.  The best solution would be to buy a chip with a PPC core already included, but they start at over $800 in volume.  We're in between a rock and a hard place here, sadly.  I would sooner recommend sticking it out with the original 68000 and keeping the price reasonable than take such a risk at this time.

[downix]

jkonstan wrote:
OS4 is PowerPC based; thus, a PowerPC solution is best practical option.

OS4 is just OS 3.1 ported to PowerPC, so I understand, I'm sure folk with more know-how can be more clear on this.  But, being that, there is no practical reason for locking it onto PowerPC.  Infact, I'd almost say it would be smarter to keep the OS on m68k and use a fast JIT emulator to bring it to other CPU's, a la Amithlon.

[downix]

HenryCase wrote:

Finally, read the last paragraph of the first post here:
http://www.power.org/forums/viewtopic.php?t=712
Free SPARC and MIPS clones of PPC chips exist! Tried to find them, no luck so far, but I would imagine it's a cheaper solution than the Virtex-4 one. If we made our own SPARC or MIPS core we could even integrate the MiniMig (complete with 68K CPU processes) into one chip capable of running OS4, given enough time.

No, that's not what he said.  He said that free clones of SPARC and MIPS CPU's exist.  You can find both on the opencores.org website.  SPARC is an open standard, Sun even released the code to their high-end UltraSPARC T1.  MIPS, however, is not, and true clones are liable for lawsuit due to patents.  Same with PowerPC.

[downix]

HenryCase wrote:

downix wrote:
No, that's not what he said.  He said that free clones of SPARC and MIPS CPU's exist.  You can find both on the opencores.org website.  SPARC is an open standard, Sun even released the code to their high-end UltraSPARC T1.  MIPS, however, is not, and true clones are liable for lawsuit due to patents.  Same with PowerPC.

Damn. Well, thanks for clearing this up for me downix.

Slightly OT, I was looking around the opencores.org website yesterday, came across this device:
http://www.opencores.org/projects.cgi/web/usbhostslave/overview
If the 68k core is integrated into the MiniMig FPGA, freeing up enough I/O capacity, this seems like a cheap way of adding the much requested USB functionality to the MiniMig. Of course we'd have to write our own drivers for it.

Incidentally, wouldn't there be legal repercussions if the 68k chip was emulated in FPGA form? And could we be sued by the A500 custom chip patent holders (I doubt OCS is open source)?

Unless you have a beefy CPU (like a 25Mhz 68030) then USB would still bog you down.  Now, that being said, if you could expand the MiniMig's RAM, you could add an embedded controller for it, and handle it like a firewire for data transfers, and like PS/2 for mouse/keyboard, but then you'd need a bigger FPGA.  I've used that core in a few projects, never had an issue with it.

The OCS patents expired a few years back.