I just noticed a new video on majsta site :
http://www.majsta.com/modules.php?name=News&file=article&sid=65Shows web browsing on a600 with his new accellerator!
Impressive stuff.
Watching made me wonder (I know we touched on other things that might be possible to add to the fpga core)
It made me wonder if perhaps by hooking into the amiga's datatypes image decoding libraries - if it would be possible to have hardware accellerated image decoding done on the FPGA? I've no idea if this is feasible or not - but i thought it might be a topic worthy of discussion. This would be a major speed boost for web browsing and image viewing on the Amiga and one thats not so dependent on CPU speed if it could be done by a dedicated part of the FPGA.
Would love to know if this is possible!
Nick
