So far everyone seems to have missed the boat on this topic! :laugh1:
The biggest problem with this hack is not the 2x CPU speed, rather it's the 2x E clock speed.
The E clock is generated by the 68000 CPU and supplied to the CIA chips for a timing reference.
The easiest fix would appear to be to divide the E clock by 2. But there is still some inaccuracy with this approach in that the E clock is not a 50/50 duty cycle clock, rather it's a 40/60 duty cycle clock.
The second but smaller problem is that there should be one 14 MHz wait state added at cycle termination to meet the 7 MHz 68000 timing specs. But with some moderate skew on the 14 MHz clock and some extra timing margin in on-board devices you might get by OK without the extra wait state.
Now, when you consider the time, effort and extra logic needed to do it right is it then really worth all the effort?
