Thanks for the question.
The RAS-only refreshes are handled and ignored.
The board must see RAS1 (pin 38) low and one of the CASs low, and then it will assert /CE to the SRAM. If CAS goes high (as it does at the end of a cycle), then /CE is disabled.
If RAS1 goes low with no associated CAS (whenever a refresh occurs), /CE isn't brought active.
I've checked the timing (and propagation delays) and watched the amiga's latches in relation to make sure that the card is behaving as it should. (ie made sure data is stable and held for the appropriate durations)
Regarding the addressing, the SRAM uses a full address bus, but the one coming from the amiga is multiplexed. So, I latch the row address (first 9 bits) upon a falling edge of /RAS1, and latch the second 9 bits on a falling edge of either CAS.
I know I glossed over this earlier. Don't forget I've done billions of error free memory accesses in a row without even a single error. 
Thanks
I wasn't aware that Fat Agnus was performing a RAS only refresh. Did you confirm this with your logic analyzer?
Since your de-multiplexing the address' then you need to delay your SRAM CE long enough for the SRAM address inputs to be stable.
The normal time it takes to reset a 7 MHz 68000 and then execute some Kickstart code before a Chipmem access should be more than enough time to meet the start-up time requirements of the slowest SRAM.
The ROM overlay function should not be a problem as long a your circuit properly ignores the refresh cycle (That's why I mentioned it).
Logic probe loading may correct a problem with address' (or data) being stable at latching time. Some low value in-series resistors or high value pull downs may help here but a delay in latch timing may also solve the problem. So you might want to check your SRAM CE timing again.
