Well you pretty much have it explained. Yes, the Amiga was designed to allow Chip bus sharing via interleaved memory cycles with the primary DMA controller (Agnus or Alice). However, the CPU has low priority on the Chip bus. It's all depends upon the Screen mode and overscan usage which require more DMA bandwith.
This is completely different from SCSI DMA controllers which master the bus and totally prevent CPU access until their transfer is complete. 68040 and 68060 were designed to function as low priority bus masters and can still operate from their internal caches durring DMA. However, 68030 and earlier do nothing accept wait for the DMA controller to release the bus.
The only issue you have not addressed is bus arbitration. It's the basic protocol used by the CPU and alternate bus masters.
