Cyberus wrote:
Hi,
1) PPC - The Power PC cards are accelerator cards for the A1200 (and A4000?) right. On board these cards are Motorola chips later down the development line than the 68k series of processors? These chips were also used by Macs?
Do you want the short answer or the long one?
68000 to 68060 are CISC CPUs. Complex Instructon Set Computer (I thought the last C was for Code, but wasn't). The Amiga OS works on any of these CPUs (68010 was a problem, though.) The 68060 had a problem as well. It had to have a library externally available, because moto didn't put in the entire floating point math unit (FPU) inside. Power PC 603e and 604 and 604e are RISC chips. Reduced Instruction Set Computer. They were used in macs. And on the Amigas, I believe that, EVERY acceleator that has been made to date included a 68040 or 68060. No version of AOS can run on a RISC, until now. What was done, was the computer would start, and the 68040 or 060 would run AOS, then a program would catch some pieces of AOS that were re-written that could work on the PPC, and only that was run there, then control returned to the 68040, or 060. Then some compilers were released that could make a standalone program run in the PPC CPU only. That was when you REALLY saw a speed increase. Remember, the OS was still on the 040, or 060.
The AmigaOne uses a G3 or G4 (those would have been 605 and 606, but they quit using that number scheme). AOS 4.0 is the first, entirely RISC, implementation of the OS (as well as morphos). IT WILL FLY!!! Compatability with old software will be achieved by looking at an instruction, then running RISC instuctions that produce the same result as using an instruction on the 68000 series. AOS 4.0 is written by Hyperion who have total access to the original source code of every release of Amiga OS. As well as access to all the schematics of the custom chips (rumour is, some don't exist anymore).
I don't know how morph os came about. The full access to source is why I am glued to AOS4.0, and will persevere all set backs.
Personally, I am dissapointed with the RISC concept. It uses smaller instructions than CISC. The idea being, one instruction, one clock cycle. RISC insructions are 1, 2, 3 (and maybe even 4, not sure) instructions long, and some engineers felt that, well, a RISC instruction doesn't necessarily do anything in 1 or 2 of the 2 or 3 instructions. So let's make 1 instruction do 1 action. Good sentiment, but I don't like it because, Amiga code was exceptional, and compact. Now, I feel, it will be unnecessarily bloated because 3 insrtuctions will use 3 bytes on disk and (3 instrutions * 4 bytes) = 12 bytes in ram (someone help me, am I right?).
I believe I answered most of what you were asking about.
Any corrections are most welcome.
Amiga! On the rebound!
