I know it has been written in some other thread but how much of the FPGA Spartan 1600 used in the FPGA Replay is used by the plain 68000 CPU ?
Need the number to figure out if another CPU implementation is realistically possible.
Sure it's realistically possible. You'll need to figure out which family of FPGA you are interested, particularly which vendor, and download the tools for that vendor. (Xilinx ISE Webpack or Altera Quartus 2, etc)
Now get the HDL for your baseline, which might be the TG68 VHDL code.
Set up enough of a project to be able to synthesize. As you aren't actually making a product, and only want FPGA utilization report, you may not need to do everything that a full product project may need to do. I'm not sure if you'd need to assign pins in the constraints file or anything or not.
Run synthesis until you've weeded out the errors and important looking warnings, and look at the report. I've not looked at Altera tools yet. Xilinx gives you utilization % of LUTs, flops, clocks, etc. You may have to assign TG68 clocks to FPGA clocks, not sure.
If you can't do that, then someone else should be researching if it's practical to do more than plain 68000, such as Yaqube and Mikej, which I think they are already doing. Or the Natami guys, who may or may not still be doing exactly this project. Or Suska guy. I believe it's very doable, and just a couple days ago started thinking about an FPGA on a PGA carrier to replace 68060 which are so hard to find the good ones now. (or any other 680x0, but earlier ones have 5V issues to fit in too)
