FPGA Replay Board

[billt]

I guess it must be the developers preference. "Easier to maintain" probably means "Easier for me to read & change". Heh Verilog ain't that bad once you get used to it

I'd say it's just developer preference. In my case, Easier to maintain would mean I'd convert the CPU softcore to Verilog. VHDL is IMHO icky and gross but I like Verilog.

But having everything in a single language means one could simulate with an open-source simulator (either Icarus, Verilator or GHDL).

[billt]

mikej, As you seem to work with ASIC design. Do you think it's realisable to create a design consisting of a plain matrix of CLB elements? as way to an open source FPGA chip?

You mean to make our own FPGA silicon? That's an enormous amount of money. You don't necessarily need a lot of people, I've seen it done with 4 or 5 chip designers, 9 or 10 software guys to make the place/route tools etc. And you'd need some legal to make sense of existing patents to keep yourself out of trouble. But the EDA tools are HUGE expensive. The legal part is likely also HUGE expensive. And you'll also likely need a few years of work time for anything to happen. I'm not sure it's worth the trouble...

[billt]

The first FPGA was put on the market in 1985 so any patents for a plain matrix setup is likely obsolete many times over (5yrs). So for that part one can just make a simple circuit and duplicate it over and over. It won't be as good as the current topsellers but the point is to make a huge matrix available without the entanglements that currently exists.

As for software there already exist some really serious tries to replicate the existing routing software and that's with a unknown chip layout. Making the same effort for a simple and known layout should be way easier. Besides there are a lot of people prepared to write open source software..

A configurable logic matrix chip without ties to corporate directions and without ties to a specific platform would be of significant benefit in the long run.

Getting anything designed will require a lot of money from someone. I can't imagine being completely free of corporate direction type issues, whatever you think those are. And I think there's enough FPGA and other chip patents to wade through and avoid that it would be a big effort to stay clean. And you could still get sued just for the giggles of it and have to pay for that fight, valid attack or not.

In the time it would take, we could be making interesting cores for existing FPGAs, I think that makes way more sense. I'd rather play with an FPGA Replay or other existing board, improving Minimig and adding new stuff, than spending 3+ years making a chip, debugging it, debugging software, and then start making fun cores and stuff.

I've done silicon layout of FPGA chips. Spent 8 or 9 years doing that in a small team. In that time was two technology generations based on an existing archtecture. I don't know how long it takes to define the architecture and code up RTL of that. I do know it takes a LOT of time just for layout implementation of whatever architecture, and I have an idea of how much the tools cost and how much masks cost, I know it takes a LLLLLLLOOOOOOOOOOOOTTTTTT of money from someone. Others are free to go at it, but I think the big money guys at Xilinx and Altera etc. are way better suited to making FPGA silicon. I can't imagine seeing such a project happen, just because of the money if nothing else.

I'd be interested to see if anyone ever does such a thing, but I expect I'd still prefer Xilinx/Altera big corp chips due to better performance and features.

[billt]

You can't under any circumstance tinker with NatAmi's HDL source code. Should it be released it's still locked to a specific FPGA vendor.
With FPGA Arcade ASFAIK, the HDL sources will be released for tinkering, hacking and feature proofing.

HDL isn't so particular to a particular FPGA vendor. There's not different versions of Verilog language from one company to another, nor different VHDL language from one vendor to another.

Depending on if they make heavy use of a particular FPGA feature, you may have to port to equivalent feature in another chip, such as if using internal memories for buffers or FIFOs or something, or some hard-coded maths circuit. Not really the end of the world there though.

Minimig's HDL is already on multiple FPGAs from multiple vendors - Xilinx and Altera, no?

Natami: Closed design
Replay: Open source (with 68k AROS)

Replay the board is open-source, such as schematics and layout files? Or do you refer to Minimig port to this board being open-source, not the board itself? (Minimig is GPL, I hadn't heard Mike planning to give away his board design)


On a slightly different note, the other day I stumbled across another open-source Amiga,
aoOCS   http://opencores.org/project,aoocs  which uses Wishbone bus and thus can connect to a lot of OpenCores thingamies. Neat!

[billt]

True, but they use AHDL which is vendor specific. It's way more work than just porting it. Should it ever be released.

One should however note that the sources for FpgaArcade are still closed, asfaik.

I wasn't aware of AHDL. At work we use Verilog, and some customers bring in VHDL. But we're an ASIC company converting to a microcontroller company, we got out of FPGAs years ago and never had our own company language for those. Interesting they chose this, but it's their choice to make. I'd be curious to know why if they're ever for talking about such things, but obviously I haven't kept up on Natami forums to know about the AHDL thing. I wouldn't have chosen a lock-in language, as I'd want as much flexibility as I can get in case the future provides some opportunity to change FPGAs or go ASIC.

This does make any potential future port more work, yes. Perhaps like porting a program from C++ to Java.

Minimig for FPGAArcade board doesn't need to release sources until binaries are published. I wouldn't expect those to come out until they're satisfied it's working reliably.

[billt]

You can buy an 060 for about $40.

Where from?

[billt]

AlexH "MC68060RC50, with the Mask 1E41J." are the ones to go for apparently..
Overclock and run cool.
I'll make some inquries in China next time I am there, they probably have buckets of them hidden away.
/MikeJ

I'm trying and failing to find a post I think from AlexH about having some laying around. The 060s I see on Ebay today look like "working" pulls and all seem to be in China. There's RC60s now too which I find interesting, back when I was looking for one some years ago there wasn't an RC60, only an RC50. I'd definitely only go with an RC part whichever one, I definitely don't want to leave out any features.

[billt]

I think Atari-ST, Macintosh 68k, 80386+VGA+SB

Have you checked out Suska? Anyoen intrested in porting to FPGA Arcade? (It's the Atari equivalent of Minimig core from the sounds of it)

http://experiment-s.de/en/atari-ste-in-a-chip/

[billt]

And as far as size limitations, I wasn't suggesting this:
"it'd be pretty sucky to put in a replacement ROM/flash on an A500 and  have to boot a second stage image from floppy before you can boot a disk"

I was thinking more toward a larger banked EPROM that could appear as a 512KB or 1MB ROM but hold more when booting.

Well, what abotu a dual-stage ROM boot? Have the actual aros-start image highly compressed in there. Initial boot uncompresses that into RAM and then does a softkick-alike thing to then boot that RAM image of the firmware?

I suppose that requires a known available amount of RAM at a known location, which may or may not be true for all Amiga motherboards/acceleartors. Has this been discussed anywhere for me to read up on?

[billt]

Try it on real Amigas?

I assume you mean to try the softcore CPU in real Amigas. Check this out:
http://eab.abime.net/showthread.php?t=52364

[billt]

A Zorro bus would be a complete waste.  Nobody is producing any Zorro hardware and why would you want to connect a 20 yr old Zorro device to this system when you have several other interfaces that are modern and more efficient?

Educational purposes only I suppose.

http://opencores.org/project,zorro_to_wishbone_bridge

[billt]

@trekiej, If you mean an FPGA with capacitity for more gates etc.. the answer is that it will require a new board spin as the BGA-solder balls underneath are really tightly packed and an adapter would be a real pain.

I know that Xilinx has a scheme where models with "more stuff" can be selected for the same package and pinout but the XC3S1600 is maxed out in this respect.

Is that really true? Xilinx's Spartan3e datasheet says the 1600 comes in these packages:
FG320/FGG320, FG400/FGG400, and FG484/FGG484.
http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf

The Spartan6 datasheet says some are available as FG484/FGG484.
http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf
I guess someone would need to compare exact pinout details, voltages, etc, but the same package is a starting point for hope. And if Mike uses the 484 one. No guarantees of course.

But really, lets see what FPGAarcade 2 will have someday

[billt]

FPGAArcade is surely destined to be a fun hardware emulation platform. Not meant as a replacement computer.

And I'm sure Mike might be suprised that we bonkers Amiga weirdos want to treat it as a full computer replacement. But as soon as we became able to do Amiga stuff with it, desire began to build to have a more and more advanced Amiga from it.

Natami may be a more appropriate choice for a computer replacement, as it has a normal PCI slot. Perhaps FPGA Arcade 2 will embrace the idea and take on more of a computer replacement form. Though I think it'd me cool to put a (or some) big FPGA(s) on some standard computer module and have whatever shape carrier for that standard we want, including a full-out ATX.

[billt]

Who on Earth would want more than 640KB?

I think 128MB is fine for now until we actually see some applications being produced that require more, or at least slots that can be added to later.

But what will you do when applications are produced that require more? You're screwed.

Yes, slots are good. I like SODIMM slots. But that can be another pile of stuff to deal with, adding ability to scan modules to know what they are, what if modules report wrong spec (as I understand a lot of them did causing memory issues with A1 boards). A fixed design helps focus and debug elsewhere, perhaps a later respin will trade hardwired RAM for a mem slot.

[billt]

The main problem is space actually on the expansion board, the processor is huge!
The second problem is tracking. It may be possible to stick rams on both sides which would double the capacity. I'm just starting to look at this seriously.
/MikeJ

Some memories have dual package options that mirror each other. Then the top side chip can connect to the bottom side chip with nothing but vias. Of course that may be in the way of your decoupling caps, but they must have a solution for that. I think it's popular with graphics cards.