I find Verilog a LOT easier to learn/follow than VHDL. VHDL is more verbose, and the book they used when I was in college was horrible. There's basic files you need to include like you need include files in C, but this book didn't even tell you how to do that. So I very early on developed a (perhaps unfair) bias against VHDL, I didnt' see Verilog until years later and like it much much better in comparison.
Check out icarus as a free verilog simulator. Play with simulation to get a feel for things. Also check out opencores.org for some free verilog and vhdl IP to see what that looks like, and as a free parts library to get you started.
