"open source VHDL software" might refer to more than just the synthesis tool for a particular FPGA chip. What about simulation? Wave viewers? Linters? Logic Equivalency Check? (compare synthesized netlist to RTL source code to make sure it truely is the "same thing") Scan test insertion?
OK, there's a lot that may be overkill for an Amiga FPGA experimenter, and there may not be open-source equivalents for a lot of these things. But at least simulation may be interesting to help track down bugs.
http://ghdl.free.fr/
