Depends on the "source code". Languages such as verilog and VHDL exist to do that wort of thing, but the source code has to be in those languages. That is then "compiled" (AKA synthesized) into a gate-level netlist, which shows inverters, flipflops, and-gates, etc. which can then be put into an FPGA chip or if you're righ made into a custom chip.
You can also simulate both the "source code" (AKA RTL or Register Transfer Level code) and the "compiled" or synthesized gate-level netlist.
There are tools which are capable of importing these gate-level netlists into schematic views. But schematics imported from verilog or vhdl aren't known to be easily readable by humans. And you need to have a library of symbols available for any gate or cell that would appear in the netlist.
There's also some attempts to do this sort of thing with C or C++. SystemC may be more like that.
Google for "HDL" and see what you learn. HDL stands for Hardware Description Language, which includes verilog, vhdl, systemc, and others.
