PowerUP all over again. Amiga did that in 1997 already, and this is very far from being as useful as SMP.
Actually, for once, no. The PowerUp model is not remotely close to finding some nasty cooperative-style hack* to use the second core in, for example a dual core processor. Firstly, you aren't dealing with two different types of processor and secondly such processors implement hardware cache coherency between the cores. They have to - it would be utterly absurd in any SMP model where a task is moved onto a different core as part of regular task scheduling only to discover the L1 looked totally different than when it last ran. Usually, the only contention in multicore processors is when two cores need to access the same cacheline (and if they are both just reading it, that's not necessarily a problem) and there are well established hardware protocols for that too. I think the PA6T uses the MOESI strategy or something very similar.
*Of course, this is not SMP, or even AMP.
