Duly noted. Even though you have transplanted an additional foreign brain from a totally different species and likewise a foreign display system, all communicating with the original carcass over transplanted foreign busses.
They share the same bus into memory. Logic on the board handles any differences between m68K and PPC's local buses.
Having both a PPC and 68k, would describing at as having a multiple-personality disorder be more appropriate? That might explain why it slows down every now and then: the two CPU's are fighting over who will be the dominant personality.
This is what caches are for. When you read from memory and you get a cache hit, no actual bus activity need occur. When you write to memory and you have copyback enabled, no actual bus activity need occur at that instant either. It'll get done some time later when the CPU decides it's the right time. When that happens, each CPU will spend most of it's time performing whole cache line transfers.
The worst performance hit in these systems are forced cache flushes on context switches. That is painfully slow. However, when you are performing a complex operation, such as decoding a datatype, one or two of those is totally hidden in the speedup you get from doing the work on a 3-digit clockspeed CPU compared to a 2-digit one.
Now, talking about actual bus contention, you have to look no further than a 68K machine without fast ram.
The original 68000 can only access memory once in every two cycles. The custom chips get it every other cycle
ideally. However, bump up the screen size, number of sprites etc and before long the DMA starts to eat into the bandwidth available for the CPU. And the custom chips will always win, slowing the CPU down. In fact, the CPU is forbidden alltogether from performing certain atomic operations on Chip RAM by the architecture.
On a 68020+, the situation is significantly worse since these CPU's can access memory every cycle. This is why a bare A1200 dies on it's arse compared to one with (pref zero wait state) fast ram fitted.