OS4 Classic, why disable the 68k ?

[itix]

I must admit that I've never really "seen" applications that ran parallel in that sense on a phase5 board - regardless which kernel or OS was used.

I am sure everyone have used PPC accelerated mpega.library or datatypes. PPC is decoding next mpega frames while 68k CPU is doing something else but of course memory bus is always a bottleneck there.

But CPUs cant run in parallel in sense they could work on same data structures simultaneously. Something like reading system structures is strictly forbidden from PPC side because it is not coherent (no, cache flush technique is not going to fix that).

[itix]

This brings us back to the original question. Well the answer is that emulating 68K code on the PPC is faster due to not having this cache flushing limitation. Even a 603e is generally faster than it would be on the real 68K, certainly if your 68K is an 040 like mine.

68k code that is executed only once probably runs faster on real 68k, though.

It's all very pie in the sky, but it seemed theoretically possible when the idea first occurred that you might be able to produce virtual DMA controllers for things like the onboard IDE, parallel port, PCMCIA or whatever and then drivers that utilise them.

Since interrupts are executed on a PPC side you would have to make some substantial changes there... and since those devices still wouldnt run any faster only advantage would be having more cpu time for idle task =P