Gulliver wrote:
I thought abou waitstates but i found several designs claimed to have Zero wait states! How? I dont know!
They're talking about read/write access cycles to fast mem not needing wait states.
Any read/writes to chip mem or motherboard chip registers will still be controlled by the custom chips, so you're stuck with their timing as to when the cycles are terminated.
You might wanna think about making the CPU clock a multiple of the A600 bus to make syncing easier.
IIRC,you're not gonna be able to make use of the 030's cache burst , cos it needs a 32bit data bus to be able to do it.
BTW if haven't already got it, get the
MC68030 User Manual from Freescale and read chapter 7 (Bus operation). The bit about Dynamic Bus Sizing answers your earlier question about hooking up the 030 to a 16 bit data bus.
There's also a section on howto use a 030 in a 020 design (such as the Frances board others have suggested)
