The memory bus of the Minimig runs at 7.09 MHz so it was the simplest solution. The CPU can access the bus every clock cycle if it's not used by the chipset DMA.
The 16-bit opcodes are executed one per clock cycle. The performance could be even better if the data bus was 32-bit wide.
According to timing analysis results both these cores can run up to 20 MHz on Spartan-3E. I will try to run the CPU twice the speed of the memory clock. And with a prefetch buffer to improve memory throughput.
24 MHz SPI, no DMA.
:rtfm: At 7.1 MHZ the bus speed would be 14.2 Mb/sec, or twice the speed of the A1200 chipmem bus: From that limitation, I wouldn't expect any significant performance gain over the current speeds. The Sysinfo speeds as indicated by Yacube 1.85..2,5 x A1200 correspond to that. Could a future Minimig AGA core perhaps take a bigger slice out of the 133 MHz DRAM bandwidth of the FPGA- replay board to allow for greater speeds (perhaps up to 68040-25 level) in the future?
