Welcome, Guest. Please login or register.

Author Topic: C64 FPGA Idea  (Read 6828 times)

Description:

0 Members and 1 Guest are viewing this topic.

Offline vidarh

  • Sr. Member
  • ****
  • Join Date: Feb 2010
  • Posts: 409
    • Show all replies
Re: C64 FPGA Idea
« on: May 08, 2011, 12:15:11 PM »
Quote from: trekiej;636500
I was wondering if some one thought about widening the bus for the 6510 processor.
Eight bit opcode and an eight bit or 16 bit operand for a fpga c64 sound interesting.


There is already a *real* 16 bit replacement for the 6510, the WDC 65816, designed by Bill Mensch, one of the original 6510 designers. It was available from 1984, and has been used in the Apple IIgs for example, and is still manufactured as well as possible to license as a core for ASICs. There's also a drop-inc 6502 compatible version, the 65802, but that's more limited for obvious reasons (no wider external bus)

Since there's been accelerators for the C64 using it too, I'm sure someone will do an FPGA version eventually if there isn't one already.
 

Offline vidarh

  • Sr. Member
  • ****
  • Join Date: Feb 2010
  • Posts: 409
    • Show all replies
Re: C64 FPGA Idea
« Reply #1 on: May 08, 2011, 08:40:50 PM »
Quote from: trekiej;636566
I would like a chameleon too.
I am wondering if a wider buss is possible in the design.


Given that the FPGA is big enough to handle the Minimig core, I'm sure it'd be possible. It's back to whether or not someone spends the time updating the cores...

Quote

I hear that the c64 has a 256 byte memory page.
It is suppose to be faster if one keeps code inside that page instead of trying to move
Address H and Address L all the time.


Well, there are a few different things: If you want to do indexed accesses, it's faster to do that in the 256 byte zero page. Also, if you cross a 256 byte boundary I believe you incur a 1 cycle cost, so you'd want to be a bit careful about the location of tight inner loops etc. (and in demo effects it'd bite you very easily for any effects that need cycle exact timing, like DYSP). That's the ones I seem to remember off the top of my head.
 

Offline vidarh

  • Sr. Member
  • ****
  • Join Date: Feb 2010
  • Posts: 409
    • Show all replies
Re: C64 FPGA Idea
« Reply #2 on: May 09, 2011, 10:35:48 AM »
Quote from: alexh;636616
Why would you want to? Surely the idea is to run as much C64 code as accurately as possible?

Widening the CPU instruction bus & data bus is pointless. All you do is introduce huge binary incompatibilities.


The 65816 managed it just fine, by starting in 6510 compatible mode and making you run a two instruction sequence to turn on the extra capabilities. For things like GEOS and GEOS apps and other non-timing dependent applications it should work fine. But of course most games etc. are likely to fail miserably.

I'm not sure the available C64 apps are really interesting enough to make it worthwhile other than for the hack factor, though.