VRAM wouldn't help with effects like dual playfield.
Sure it could, as long as the chipset can store a full row of bits from a single read, then do another read for the second playfield and combine them before moving on to the next row. It would still mean the chipset would've been able to use 100% of the bus cycles on the read-only port for display DMA, and part of the cycles on the other port (for blitter, copper etc.), and still leave more cycles free for the CPU.
