Hello
From time to time I see someone reporting that the interrupt handler routines, before exiting,
should write TWICE the register INTREQ to clear the interrupt request. Otherwise with 040/060 system
interrupts are executed twice.
Example
InterruptLevel3
move.l xxx,BPL1PT
...
move #$0020,INTREQ
move #$0020,INTREQ
rte
This solution of does work, but on my 040 other, more elegant solutions work too: for example it is enough
to execute a NOP before the RTE, since the NOP force the CPU to actually perform the write to the register
before executing the RTE (040 and 060 can defer the actual write to memory after performing other instructions
in the pipeline). Onother solution that work is to simply read a value from memory after the write to INTREQ.
So, in my programs I always use:
InterruptLevel3
move.l xxx,BPL1PT
...
move #$0020,INTREQ
NOP
rte
However recently I saw the source code for "The Player" P6.1.3 use BOTH the double write to INTENA AND the NOP.
So I wonder, is there some strange configuration where the double INTENA write is really needed?
And if yes, can you explain me why?
The Dark Coder
