All of this back and forth about pros and cons seems counterproductive.
I'm in the camp of people who aren't interested in FPGA accelerators until they can do at least what a real m68k can already do, and that means an FPU and an MMU. I haven't added anything to these threads because nobody is talking about a compatible FPU and a compatible MMU in these products, but the naysayers and the apologists going back and forth are just making this all too annoying.
What I would genuinely like to see would be real, technical information about the technical roadblocks for a proper compatible implementation.
As far as I'm concerned, there are so few differences between the m68040 and m68060 that a core could and should be a superset of both. An option can be set at boot time to determine if the exception stack and status register should match one or the other. Options to enable / disable superscalar and branch folding in the PCR and CACR are a superset of the '040, and 64 bit instructions from the '040 can be implemented instead of trapped without breaking anything.
The FPU could easily be a superset of m68881/m68882/m68040/m68060 since anything emulated by the M68060SP can just be made in to directly working instructions.
With regards to an MMU, there are many differences between the m68040 and m68060 MMUs, so one would have to be chosen, probably based on whether there's enough support for the '060 MMU model. The access error stack frame is more detailed in the '060 MMU, the '060 has the PLPA instruction instead of PTEST to translate logical to physical addresses, the cache modes for the TTRs are different, and so on.
I wish I knew more about FPGA development because I think it'd be interesting to try to implement an MMU. It'd certainly be challenging!
