Personally, I am dissapointed with the RISC concept. It uses smaller instructions than CISC. The idea being, one instruction, one clock cycle. RISC insructions are 1, 2, 3 (and maybe even 4, not sure) instructions long, and some engineers felt that, well, a RISC instruction doesn't necessarily do anything in 1 or 2 of the 2 or 3 instructions.
There isn't any real distinction between RISC and CISC chips anymore. Pentium Chips are just as RISC as G4's, and vice versa. We have reached a middle ground and obliterated the extreme camps that gave the distinction any meaning in the first place.
