natami

[SamuraiCrow]

Re:The NatAmi team

I was reluctant to join the team because I knew I couldn't afford to buy a prototype NatAmi with the 68060 board included.  Now just as I've gotten a source of income and can buy one, Thomas has gone underground.  I don't blame him at all for doing so.  Gunnar was really hard on Thomas for not accepting help with the chipset design and not doing so in VHDL instead of AHDL.

What resulted in the "too many chiefs, not enough indians" situation was that there were mostly software guys on the team.  When it came time to implement the hardware, Thomas wanted to do the chipset himself as the icing on the cake.  This is what lead to the current situation.  An Amiga without an OCS compatible chipset is no Amiga at all, IMHO.  There are still missing features on the NatAmi chipset cores to this day.

While I have a 2-year degree in electronic engineering technology, it's not enough to be able to figure out all of the intricacies of a hardware descriptor language.  I had hoped to write drivers for the chipset but started running into insufficiencies of the AmigaOS Graphics.library and not much of a solution in AROS 68k.

While it has been observed that a FPGA is an emulator, it is not a software emulator.  It is much more massively parallel than a multicore CPU and can run things much more efficiently.  More importantly, it is a step toward a baked chip and even an ASIC if the market will bear the design costs.  What the market wouldn't bear, I'm convinced, is both the NatAmi and FPGAArcade boards at the same time.

[SamuraiCrow]

It was my understanding (could be wrong) that the FPGA on the FPGA Arcade wasn't as big as the one on the Natami.
I didn't think there would be enough gates to fit what Natami was trying to do???

The bigger problem with porting the NatAmi code from the Altera Cyclone IV to the Xilinx Spartan 3 is that it can't mix with the MiniMig core at all.  MiniMig is GPL code while NatAmi is closed-source.  Also, MiniMig is programmed in VHDL I think, and the NatAmi chipset is coded as AHDL which only works on Altera FPGAs.  Porting from Altera to Xilinx is possible but requires conscious effort to fix the code conversion problems from the converter.