Well if you can't do an 060 FPGA core for less than an actual 060 chip on an accelerator card then don't. The guy asked a simple question.
As to 3.5mhz chipset<----?? The bus is 7mhz, so is the chipset (well actually the whole thing is run at 28mhz I believe and clocked down to 7.09 or 7.14mhz IIRC)
That reference was referring to the A500 assuming it has all Chip RAM and no Fast RAM in its defualt configuration. The A500 did not have 70 nanosecond memory capable of 14 MHz bus access and therefore the CPU and chipset had to split the 7 MHz bus speed between themselves taking every other clock cycle for each.