If Genesi uses the MV64361 controller then why do the
only have one Gb ethernet port, and why no PCI-X slots?
Or does the MV64361 only have one PCI-X controller?
And wasn't it supposed to have a 200Mhz fsb and a DDR400 controller?
I'm guessing that this is due to cost considerations,
which is nice in a way but it has put it off my list of desireable hardware.
The sad part (for me) is that I was looking forward to buying it if
Genesi could get OS4 ported to it, now I guess that I'll
have to wait untill the A1-light is released to get a nice
speced and priced mobo
(or the peg-III if OS4 will be available and the price is right).
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From:
http://www.marvell.com/products/communication/discoveryII/MV64360.jspThe Discovery II MV64361 controller offers a 72-bit DDR
memory controller with a 183 MHz clock rate (366 MHz data rate),
on-board 2 Megabits SRAM, dual 32-bit PCI/PCI-X interfaces,
PCI bridge and arbiter, two 10/100/1000 Mbps Ethernet controllers,
two multi-protocol serial channels, and TWSI and interrupt controllers.
Key Features
High-performance controller for PowerPC-based communications systems
* 64-bit 133 MHz 60X/MPC CPU bus interface
* 72-bit (64-bit with 8-bit ECC) 183 MHz DDR SDRAM controller
* Dual 64-bit 66 MHz PCI /133 MHz PCI-X interfaces (for MV64360)
= >* Dual 32-bit 66 Mhz PC/133 Mhz PCI-X Interfaces (for MV64361)
* Single 64-bit 66 Mhz PCI/133 MHz PCI-X interface (for MV64362)
* Advanced internal crossbar fabric
* 32-bit 133 MHz peripheral device bus interface
Integrated 2 Megabits SRAM (MV64360 and MV64361 only)
Advanced communications unit
* One 10/100/1000 Mbps Ethernet controllers with packet filtering and priority queuing (for MV64362)
= >* Two 10/100/1000 Mbps Ethernet controllers with packet filtering and priority queuing (for MV64361)
* Three 10/100/1000 Mbps Ethernet controllers with packet filtering and priority queuing (for MV64360)
* Two Multi-Protocol Serial Controllers (MPSC)
64-bit PowerPC CPU bus interface
* Motorola MPC750, 755, 74xx and IBM PPC750, 750CXe, 750FX processor support
* 60x and MPX bus protocol support
* 133 MHz CPU bus frequency (2.5v or 3.3v configuration)
* Configurable cache coherency
* Supports split-read transactions with out-of-order completion
