New type of accelerator design?

[lapeno]

I personally like the idea of a new style of accelerator. Nowdays you can only buy 2nd hand accelerators and they might not work.
I don't think about a big gun like PPC or faster processors. I beleive the old Amiga systems must stay 68k based so a 68030, 68040 and 68060 based accelerator is a good idea.  
The Natami project is very good , I like it but that is not our much loved old HW. I am sure I will buy one but beside that I will always have the A1200.

One of the main drawback of the A1200 is its 14Mhz local bus. You can design a fast accelerator but that will always have to talk to the motherboard using 14Mhz clock driven protocol. That is why if you make different tests with different  accelerators the CHIP ram read and write time is nearly the same for all. An accelerator card itself is a small computer which is fast on its own board but access to outside (towards the A1200 motherboard) is slow.
This however doesn't mean that we have to give it up!

I started to think on a new design which is using FPGA for the main bus driver plus memory controller logic and have SIMM modules (or even DIMM SDRAM) as memory. CPU would be a 68030 040 or 060 but in order to make a twist on the design and create something new I would put 2 CPUs, a 68030 and a 68040/60 on it. During power on the system would startup with the fastest CPU but if you would hold down a key a menu would appear where you could choose between the onboard 020, the accelerator's 030 or 060 CPUs. Just like in WinUAE you set the CPU type. After you have chosen the system would reboot and startup with the chosen CPU.
One more important thing would be that if you would choose the motherboard's 68020 as CPU then you could have 8MB of Fast RAM from the accelerator card (even if you have a 128MB SIMM on it).

I beleive it is possible and even if this would not make money it would be a good experience to create it. I don't know whether it will ever come true but I started to investigate the hardware docs and how the Amiga bus system works. I will make some feasibility studies and develop some part of it (e.g. DRAM controller, A1200 motherboard local bus bridge). If any of you have good, unpublished or rare doc about the A1200's inside please share that with me!

Thanks

[lapeno]

I would not bother emulating he 68k CPUs when they are available still (even if they are second hand). My plan is to use CPLD or FPGA to create the bridging device which is between the A1200 and the 68040/60 CPU. Towards the 68040/60 it is a bus arbiter while towards the A1200 motherboard it emulates a 68020 CPU's bus cycles. Beleive it or not the  A1200's Channel Z port is not a magical unknown area. You can find useful information on it if you read docs carefully.

For me the Amiga is the 68k architecture and not the PPCs. I don't want graphic card or any other CPU that is not 68k compatible. All I want is faster calculation and RAM. I don't want to make money out of this, I am just interested in FPGAs and digital circuits and this seems to be an interesting project to have fun.

[lapeno]

SDRAM and later memory modules became 64 bits wide which complicates a bit the bus design between the 32 bit processor and the RAM. It is interesting however that the operation of synchronous RAM (e.g. SDRAM) is much more simpler than an asynchronous SIMM's. SDRAM would be an ideal choice for the accelerator but this 64bit wide operation must be solved somehow. I don't want to waste half of the capacity of one module just because the design is simpler that way.

[lapeno]

Interesting ideas... It is good to have this brainstorming, maybe someone will use these ideas in the future.
I however still think that a normal 68k CPU board with 512MB SDRAM, a 030 and a 060 processor on it would be much more realistic. CPU could be selected on boot menu and in addition probably USB and Ethernet support could be added to the FPGA if there is space left in it. Next development step could be to replace the CPU with an FPGA based emulated 68k.

[lapeno]

I have just made some progress with planning and documentation reading. I am now concentrating on the memory controller part and found out that indeed it is not difficult to connect a 64bit wide SDRAM to the 32bit CPU bus. SDRAM modules use mask pins (DQM) with which you can easily mask out the upper or lower 32bit data based on address.
Here are some of my specs:
1. Using PC133 SO-DIMM memory modules (1 maybe two SO-DIMM slots)
2. Supported RAM modules 32MB,64MB,128MB,256MB,512MB which gives in theory 1GB max memory with two SO-DIMM slots. These modules are very cheap nowdays as second hand.
3. No burst mode due to lack of L2 cache. Next design will have 128K L2 cache.
4. 3.3v board using 68060 CPU
5. One old FPGA for 5v interfacing with Amiga, one new FPGA for memory controller and additional interfaces
6. possibility for future extension with 10/100 ethernet and USB 2.0 support on 2nd FPGA.
7. written in VHDL