The real issue, from memory, was cache coherency due to a limitation of the Articia chip. This would only mean that the cache is flushed before a context switch.
That's nonsense. The broken articia cache coherency affect DMA transfers (cache isn't always invalidated, thus as a workaround with CachePreDMA/CachePostDMA is needed). Normally with fully cache snooping hardware (such as Articia was supposed to be), no such CachePreDMA/CachePostDMA magic is required.
