RISC CPUs were conceived to simplify the development of new CPUs with higher clock rates compensating for the relative lack of performance compared to similarly clocked CISC processors.
The idea was to simplify the design as much as possible to
1. make room on the chip for larger register and cache storage
2. get rid of microcode
3. introduce pipe-lining
By the 90's moore's law allowed CISC to use some of the RISC techniques & RISC became more complex. It would be great if you could spin up a 200mhz 603e in an FPGA, but 1. it's probably going to need a better FPGA, 2 its going to need someone who cares about PPC enough to dedicate that much of their life to doing it.
