VHDL and Xilinx Software Question.

[mboehmer_e3b]

Is it possible to state how I want the pins to connect to my code? During schematic capture it seems to be possible.

You must supply a User Constraint File or use the GUI to define the pins.

An UCF is included as source file like any other VHDL file, and can carry things like

NET "BR"       LOC = "P164";

In your top level VHDL file you can add the corresponding I/O structure on your own, like here:

OBUF_BR: OBUF
generic map(DRIVE => 8, IOSTANDARD => "LVTTL", SLEW => "SLOW")
port map(I => ZIII_BR, O => BR);

or you let the compiler do this job, and you will have to define I/O properties in addition inside the VHDL file.

The first solution gives you the possibility to define some parts of the I/O standard as generic statement (like maximum driving current, for example).

Michael

[mboehmer_e3b]

I have a Xilinx X board with a Cool Runner II chip.
It has ISE9.1 if I remember correctly.

Which is - basically - a Philips CPLD family, but a nice one :-)

Hope you get your problem solved - the Xilinx software sometimes is a mess, especially in more complex projects there can be a spontaneous scrambling of the project file, which can cost you hours to recover (make snapshots when possible).

Take also care when upgrading - sometimes an upgrade triggers the scrambling...

Michael