The theoretical maximum throughput of the 8 bit clockport is 3.5 million bytes/sec but this will never be achieved without DMA.
The clock port is 8 bits wide, and hangs off the 14 MHz 68020 bus. It takes 4 clock cycles to access this port so 14/4 = 3.5 Meg but I am unsure if you need to add another 4 clock cycles for MC68020 operation, if so this would reduce the bandwidth to 1.75 MByte/sec. My A1200 and logic analyser are too far apart to check this
I collected some note, a long time ago and put them on Aminet at
http://de5.aminet.net/hard/hack/clock_port.txtHave fun,
Ian
