Additional clockports for the A1200 ?

[Stedy]

A clockport device can only reside at these addresses, nothing else:

$D80001, $D80005, $D80009, $D8000D, $D80011, $D80015
$D80019, $D8001D, $D80021, $D80025, $D80029, $D8002D
$D80031, $D80035, $D80039, $D8003D

Whilst you could generate more by perhaps multiplexing the 8 data bus pins, you would break existing software drivers.

Also bear in mind that the maximum, theoretical, throughput of the clockport is 2.8 MByte/sec but is is CPU not DMA driven.

[Stedy]

@sparky

The design you have, does it look like this?


I forgot I had this.

This required a connection to the Kickstart chip to provide the extra address decode needed.

I also found a picture of the original quadroport here: http://amiga.resource.cx/gallery/Quaddddroport.jpg

Bye

[Stedy]

I did not draw it up, Daedalus/Robert Cranley did, see the title box!

I gave him some help and advice for the design a while back and had a copy in my posesssion. I would need to check with Daedalus if it can be released on Aminet, I will check IRC later on.

Be warned, the pinout is not as you would expect. Pin 22 of that schematic is pin 19 of P9B, pin 21, Pin 20 of P9B and so on (numbering from bottom to top).

Pin 37 of U6B is A14 and Pin 36 is A15. These decode a $4000 offset from $D80001, making the second two ports (CN3 and CN4)  appear at $D84001, the same as for a Quadroport.

This design would only accept 4 devices that need 8 address locations each.

While you are at it, design a version to fit over the 84 pin Gayle PLCC chip, then A600 users can join in!

Have fun,

Ian

[Stedy]

Hello,

The design I posted had a problem with the Interrupt handling, all the IRQ lines were tied together! So with 4 devices, if 1 signals an interrupt, it would fight the other 3 IRQ lines!

Also the original design does do the address decode for all the quadroports addresses, $D80000, D84000, $D88000 & $D8C000.

I redrew the schematic with the IRQ logic and put it here:
http://www.ianstedman.co.uk/Downloads/clockport_expander.png and as I had a bit of spare time, the PCB design is here:
http://www.ianstedman.co.uk/Downloads/clockport_expander-pcb.png
If anyone wants the Eagle CAD or Gerber files, I will put them online.

[Stedy]

@Doobrey

Actually you just found my deliberate mistake!  :-D

I should have used _SPARE_CS not _RTC_CS for the address decode, that address space is taken up by the Real time clock in your accelerator! I will upload the revised schematic tomorrow.

To access NET_CS would require connecting to Gayle, which could be done but AFAIK, no software would support accesses in the decoded memory region.

So Doobrey, why did you not publish your design then?

@Platon42

Interrupts are never tri-state. If they were the CPU probably have un-defined operation unless external pull ups are used.

[Stedy]

@ Doobrey

Deliberate mistake my ####  

Ok, I made a mistake, now corrected (new drawing online).

Yes, the RTC should only take the first port of the RTC_CS area.

Take a look at Cirrus Logic, their CS8900 Ethernet chip, will work in an 8 bit ISA type mode. See AN181 'Using the CS8900A in 8 bit mode.'

Have fun!

[Stedy]

@Doobrey,

For the CS8900, have you contacted
Unique Memec, UK distributors for Cirrus Logic parts?

Another option is SMSC, their 91C96, 91C100 and 91C111 will work with an 8 bit interface for the clockport.
Insight Memec distribute SMSC parts.

Both variants of my 24 bit I/O card have been built. I have tested the parallel port version and I designed a modified version for Xeron's CD1200 project. PCBs were made for the CD1200 board, not sure of current progress.

Details of both designs are on my website, with photos of the PCBs.

[Stedy]

Has anyone here (apart from E3B or Individual Designs) ever built and tested their own clockport card?

I've designed a serial card and such but as I am now an ex-Amiga user, it will not get built.

[Stedy]

@Doobrey

Stop pissing about, make an extender/adaptor board for the CPU slot, then you have a 32 bit, 14 MHz bus to play with!

It has _RTC_CS, _NET_CS and _SPARE_CS. What does the _BEER signal do?  :-)

Failing that, the two kickstart ROMS have the Address and Data bus of the 68EC020.

@Methanoid

Once there was the Quadroport clock port expander. There are designs posted in this topic but not tested.

Have fun.